mesa/src/intel
Kenneth Graunke 88309a9818 brw: Rename shared function enums for clarity
Our name for this enum was brw_message_target, but it's better known as
shared function ID or SFID.  Call it brw_sfid to make it easier to find.

Now that brw only supports Gfx9+, we don't particularly care whether
SFIDs were introduced on Gfx4, Gfx6, or Gfx7.5.  Also, the LSC SFIDs
were confusingly tagged "GFX12" but aren't available on Gfx12.0; they
were introduced with Alchemist/Meteorlake.

GFX6_SFID_DATAPORT_SAMPLER_CACHE in particular was confusing.  It sounds
like the SFID to use for the sampler on Gfx6+, however it has nothing to
do with the sampler at all.  BRW_SFID_SAMPLER remains the sampler SFID.
On Haswell, we ran out of messages on the main data cache data port, and
so they introduced two additional ones, for more messages.  The modern
Tigerlake PRMs simply call these DP_DC0, DP_DC1, and DP_DC2.  I think
the "sampler" name came from some idea about reorganizing messages that
never materialized (instead, the LSC came as a much larger cleanup).

Recently we've adopted the term "HDC" for the legacy data cluster, as
opposed to "LSC" for the modern Load/Store Cache.  To make clear which
SFIDs target the legacy HDC dataports, we use BRW_SFID_HDC0/1/2.

We were also citing the G45, Sandybridge, and Ivybridge PRMs for a
compiler that supports none of those platforms.  Cite modern docs.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33650>
2025-02-27 08:49:24 +00:00
..
blorp blorp: emit 3DSTATE_VF 2025-02-13 14:36:15 +00:00
ci anv/ci: Remove fixed test from xfails 2025-02-26 13:32:24 +00:00
common intel/common: fix mi_builder_test issue 2025-02-04 12:57:19 +00:00
compiler brw: Rename shared function enums for clarity 2025-02-27 08:49:24 +00:00
decoder intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
dev intel/dev: Call intel_device_info_update_after_hwconfig() from common code 2025-02-17 20:52:31 +00:00
ds intel/ds: rework RT tracepoints 2025-02-24 08:08:02 +00:00
executor intel: Initialize upper 32bits of drm_xe_sync.handle 2025-02-02 21:34:45 -08:00
genxml anv: Support putting image base address and image params in surface state 2025-02-23 15:16:51 +00:00
isl brw: add support for texel address lowering 2025-02-23 15:16:50 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf intel/perf: add new perf consts to support more metrics 2025-01-16 00:01:56 +00:00
shaders intel: output a depfile with mesa_clc 2025-02-04 00:10:01 +00:00
tools intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
vulkan treewide: Switch to nir_progress 2025-02-26 15:19:53 +00:00
vulkan_hasvk treewide: Switch to nir_progress 2025-02-26 15:19:53 +00:00
meson.build intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00