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732cfa525f
Prevent drawing outside the viewport when viewport size is smaller than framebuffer size. v2: (Jason Ekstrand) - re-emit scissor on viewport change - do the same calculations for other platforms Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5515 Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13594>
481 lines
19 KiB
C
481 lines
19 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "vk_format.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#if GFX_VERx10 == 70
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static int64_t
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clamp_int64(int64_t x, int64_t min, int64_t max)
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{
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if (x < min)
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return min;
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else if (x < max)
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return x;
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else
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return max;
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}
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void
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gfx7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
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uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
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const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
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const VkViewport *viewports =
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cmd_buffer->state.gfx.dynamic.viewport.viewports;
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/* Wa_1409725701:
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* "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
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* stored as an array of up to 16 elements. The location of first
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* element of the array, as specified by Pointer to SCISSOR_RECT, should
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* be aligned to a 64-byte boundary.
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*/
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uint32_t alignment = 64;
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struct anv_state scissor_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, alignment);
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for (uint32_t i = 0; i < count; i++) {
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const VkRect2D *s = &scissors[i];
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const VkViewport *vp = &viewports[i];
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/* Since xmax and ymax are inclusive, we have to have xmax < xmin or
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* ymax < ymin for empty clips. In case clip x, y, width height are all
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* 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
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* what we want. Just special case empty clips and produce a canonical
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* empty clip. */
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static const struct GFX7_SCISSOR_RECT empty_scissor = {
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.ScissorRectangleYMin = 1,
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.ScissorRectangleXMin = 1,
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.ScissorRectangleYMax = 0,
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.ScissorRectangleXMax = 0
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};
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const int max = 0xffff;
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uint32_t y_min = MAX2(s->offset.y, MIN2(vp->y, vp->y + vp->height));
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uint32_t x_min = MAX2(s->offset.x, vp->x);
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uint32_t y_max = MIN2(s->offset.y + s->extent.height - 1,
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MAX2(vp->y, vp->y + vp->height) - 1);
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uint32_t x_max = MIN2(s->offset.x + s->extent.width - 1,
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vp->x + vp->width - 1);
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/* Do this math using int64_t so overflow gets clamped correctly. */
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if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
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y_min = clamp_int64((uint64_t) y_min,
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cmd_buffer->state.render_area.offset.y, max);
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x_min = clamp_int64((uint64_t) x_min,
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cmd_buffer->state.render_area.offset.x, max);
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y_max = clamp_int64((uint64_t) y_max, 0,
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cmd_buffer->state.render_area.offset.y +
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cmd_buffer->state.render_area.extent.height - 1);
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x_max = clamp_int64((uint64_t) x_max, 0,
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cmd_buffer->state.render_area.offset.x +
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cmd_buffer->state.render_area.extent.width - 1);
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} else if (fb) {
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y_min = clamp_int64((uint64_t) y_min, 0, max);
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x_min = clamp_int64((uint64_t) x_min, 0, max);
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y_max = clamp_int64((uint64_t) y_max, 0, fb->height - 1);
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x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1);
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}
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struct GFX7_SCISSOR_RECT scissor = {
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.ScissorRectangleYMin = y_min,
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.ScissorRectangleXMin = x_min,
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.ScissorRectangleYMax = y_max,
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.ScissorRectangleXMax = x_max
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};
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if (s->extent.width <= 0 || s->extent.height <= 0) {
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GFX7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
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&empty_scissor);
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} else {
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GFX7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
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}
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}
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anv_batch_emit(&cmd_buffer->batch,
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GFX7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
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ssp.ScissorRectPointer = scissor_state.offset;
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}
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}
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#endif
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static uint32_t vk_to_intel_index_type(VkIndexType type)
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{
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switch (type) {
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case VK_INDEX_TYPE_UINT8_EXT:
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return INDEX_BYTE;
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case VK_INDEX_TYPE_UINT16:
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return INDEX_WORD;
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case VK_INDEX_TYPE_UINT32:
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return INDEX_DWORD;
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default:
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unreachable("invalid index type");
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}
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}
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static uint32_t restart_index_for_type(VkIndexType type)
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{
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switch (type) {
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case VK_INDEX_TYPE_UINT8_EXT:
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return UINT8_MAX;
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case VK_INDEX_TYPE_UINT16:
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return UINT16_MAX;
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case VK_INDEX_TYPE_UINT32:
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return UINT32_MAX;
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default:
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unreachable("invalid index type");
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}
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}
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void genX(CmdBindIndexBuffer)(
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VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset,
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VkIndexType indexType)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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if (GFX_VERx10 == 75)
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cmd_buffer->state.restart_index = restart_index_for_type(indexType);
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cmd_buffer->state.gfx.gfx7.index_buffer = buffer;
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cmd_buffer->state.gfx.gfx7.index_type = vk_to_intel_index_type(indexType);
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cmd_buffer->state.gfx.gfx7.index_offset = offset;
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}
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static uint32_t
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get_depth_format(struct anv_cmd_buffer *cmd_buffer)
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{
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const struct anv_render_pass *pass = cmd_buffer->state.pass;
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const struct anv_subpass *subpass = cmd_buffer->state.subpass;
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if (!subpass->depth_stencil_attachment)
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return D16_UNORM;
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struct anv_render_pass_attachment *att =
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&pass->attachments[subpass->depth_stencil_attachment->attachment];
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switch (att->format) {
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case VK_FORMAT_D16_UNORM:
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case VK_FORMAT_D16_UNORM_S8_UINT:
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return D16_UNORM;
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case VK_FORMAT_X8_D24_UNORM_PACK32:
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case VK_FORMAT_D24_UNORM_S8_UINT:
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return D24_UNORM_X8_UINT;
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case VK_FORMAT_D32_SFLOAT:
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case VK_FORMAT_D32_SFLOAT_S8_UINT:
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return D32_FLOAT;
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default:
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return D16_UNORM;
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}
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}
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void
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
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struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
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uint32_t topology;
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if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
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topology = pipeline->topology;
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else
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topology = genX(vk_to_intel_primitive_type)[d->primitive_topology];
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cmd_buffer->state.gfx.primitive_topology = topology;
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}
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
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ANV_CMD_DIRTY_DYNAMIC_CULL_MODE |
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ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
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/* Take dynamic primitive topology in to account with
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* 3DSTATE_SF::MultisampleRasterizationMode
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*/
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uint32_t ms_rast_mode = 0;
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if (cmd_buffer->state.gfx.pipeline->dynamic_states &
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
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VkPrimitiveTopology primitive_topology =
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cmd_buffer->state.gfx.dynamic.primitive_topology;
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VkPolygonMode dynamic_raster_mode =
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genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
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primitive_topology);
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ms_rast_mode =
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genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode);
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}
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
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.LineWidth = d->line_width,
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.GlobalDepthOffsetConstant = d->depth_bias.bias,
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.GlobalDepthOffsetScale = d->depth_bias.slope,
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.GlobalDepthOffsetClamp = d->depth_bias.clamp,
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.FrontWinding = genX(vk_to_intel_front_face)[d->front_face],
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.CullMode = genX(vk_to_intel_cullmode)[d->cull_mode],
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.GlobalDepthOffsetEnableSolid = d->depth_bias_enable,
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.GlobalDepthOffsetEnableWireframe = d->depth_bias_enable,
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.GlobalDepthOffsetEnablePoint = d->depth_bias_enable,
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.MultisampleRasterizationMode = ms_rast_mode,
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};
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GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gfx7.sf);
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}
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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64);
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struct GENX(COLOR_CALC_STATE) cc = {
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.BlendConstantColorRed = d->blend_constants[0],
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.BlendConstantColorGreen = d->blend_constants[1],
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.BlendConstantColorBlue = d->blend_constants[2],
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.BlendConstantColorAlpha = d->blend_constants[3],
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.StencilReferenceValue = d->stencil_reference.front & 0xff,
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.BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
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};
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GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
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ccp.ColorCalcStatePointer = cc_state.offset;
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}
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}
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
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ls.LineStipplePattern = d->line_stipple.pattern;
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ls.LineStippleInverseRepeatCount =
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1.0f / MAX2(1, d->line_stipple.factor);
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ls.LineStippleRepeatCount = d->line_stipple.factor;
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}
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}
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if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
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uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
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struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
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.StencilTestMask = d->stencil_compare_mask.front & 0xff,
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.StencilWriteMask = d->stencil_write_mask.front & 0xff,
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.BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
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.BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
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.StencilBufferWriteEnable =
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(d->stencil_write_mask.front || d->stencil_write_mask.back) &&
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d->stencil_test_enable,
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.DepthTestEnable = d->depth_test_enable,
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.DepthBufferWriteEnable = d->depth_test_enable && d->depth_write_enable,
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.DepthTestFunction = genX(vk_to_intel_compare_op)[d->depth_compare_op],
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.StencilTestEnable = d->stencil_test_enable,
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.StencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.fail_op],
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.StencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.pass_op],
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.StencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.front.depth_fail_op],
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.StencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.front.compare_op],
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.BackfaceStencilFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.fail_op],
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.BackfaceStencilPassDepthPassOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.pass_op],
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.BackfaceStencilPassDepthFailOp = genX(vk_to_intel_stencil_op)[d->stencil_op.back.depth_fail_op],
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.BackfaceStencilTestFunction = genX(vk_to_intel_compare_op)[d->stencil_op.back.compare_op],
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};
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GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
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struct anv_state ds_state =
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anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
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pipeline->gfx7.depth_stencil_state,
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GENX(DEPTH_STENCIL_STATE_length), 64);
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
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dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
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}
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}
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if (cmd_buffer->state.gfx.gfx7.index_buffer &&
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cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_INDEX_BUFFER |
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ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_RESTART_ENABLE)) {
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struct anv_buffer *buffer = cmd_buffer->state.gfx.gfx7.index_buffer;
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uint32_t offset = cmd_buffer->state.gfx.gfx7.index_offset;
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#if GFX_VERx10 == 75
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anv_batch_emit(&cmd_buffer->batch, GFX75_3DSTATE_VF, vf) {
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vf.IndexedDrawCutIndexEnable = d->primitive_restart_enable;
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vf.CutIndex = cmd_buffer->state.restart_index;
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}
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#endif
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
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#if GFX_VERx10 != 75
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ib.CutIndexEnable = d->primitive_restart_enable;
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#endif
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ib.IndexFormat = cmd_buffer->state.gfx.gfx7.index_type;
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ib.MOCS = anv_mocs(cmd_buffer->device,
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buffer->address.bo,
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ISL_SURF_USAGE_INDEX_BUFFER_BIT);
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ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
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ib.BufferEndingAddress = anv_address_add(buffer->address,
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buffer->size);
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}
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}
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/* 3DSTATE_WM in the hope we can avoid spawning fragment shaders
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* threads or if we have dirty dynamic primitive topology state and
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* need to toggle 3DSTATE_WM::MultisampleRasterizationMode dynamically.
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*/
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if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE ||
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
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const uint8_t color_writes = cmd_buffer->state.gfx.dynamic.color_writes;
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bool dirty_color_blend =
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE;
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bool dirty_primitive_topology =
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cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
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VkPolygonMode dynamic_raster_mode;
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VkPrimitiveTopology primitive_topology =
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cmd_buffer->state.gfx.dynamic.primitive_topology;
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dynamic_raster_mode =
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genX(raster_polygon_mode)(cmd_buffer->state.gfx.pipeline,
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primitive_topology);
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if (dirty_color_blend || dirty_primitive_topology) {
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uint32_t dwords[GENX(3DSTATE_WM_length)];
|
|
struct GENX(3DSTATE_WM) wm = {
|
|
GENX(3DSTATE_WM_header),
|
|
|
|
.ThreadDispatchEnable = pipeline->force_fragment_thread_dispatch ||
|
|
color_writes,
|
|
.MultisampleRasterizationMode =
|
|
genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode),
|
|
};
|
|
GENX(3DSTATE_WM_pack)(NULL, dwords, &wm);
|
|
|
|
anv_batch_emit_merge(&cmd_buffer->batch, dwords, pipeline->gfx7.wm);
|
|
}
|
|
|
|
}
|
|
|
|
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS) {
|
|
genX(emit_multisample)(&cmd_buffer->batch,
|
|
cmd_buffer->state.gfx.dynamic.sample_locations.samples,
|
|
cmd_buffer->state.gfx.dynamic.sample_locations.locations);
|
|
}
|
|
|
|
if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE ||
|
|
cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP) {
|
|
const uint8_t color_writes = cmd_buffer->state.gfx.dynamic.color_writes;
|
|
bool dirty_color_blend =
|
|
cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_STATE;
|
|
|
|
/* Blend states of each RT */
|
|
uint32_t surface_count = 0;
|
|
struct anv_pipeline_bind_map *map;
|
|
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
|
|
map = &pipeline->shaders[MESA_SHADER_FRAGMENT]->bind_map;
|
|
surface_count = map->surface_count;
|
|
}
|
|
|
|
uint32_t blend_dws[GENX(BLEND_STATE_length) +
|
|
MAX_RTS * GENX(BLEND_STATE_ENTRY_length)];
|
|
uint32_t *dws = blend_dws;
|
|
memset(blend_dws, 0, sizeof(blend_dws));
|
|
|
|
/* Skip this part */
|
|
dws += GENX(BLEND_STATE_length);
|
|
|
|
bool dirty_logic_op =
|
|
cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LOGIC_OP;
|
|
|
|
for (uint32_t i = 0; i < surface_count; i++) {
|
|
struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
|
|
bool write_disabled =
|
|
dirty_color_blend && (color_writes & (1u << binding->index)) == 0;
|
|
struct GENX(BLEND_STATE_ENTRY) entry = {
|
|
.WriteDisableAlpha = write_disabled,
|
|
.WriteDisableRed = write_disabled,
|
|
.WriteDisableGreen = write_disabled,
|
|
.WriteDisableBlue = write_disabled,
|
|
.LogicOpFunction =
|
|
dirty_logic_op ? genX(vk_to_intel_logic_op)[d->logic_op] : 0,
|
|
};
|
|
GENX(BLEND_STATE_ENTRY_pack)(NULL, dws, &entry);
|
|
dws += GENX(BLEND_STATE_ENTRY_length);
|
|
}
|
|
|
|
uint32_t num_dwords = GENX(BLEND_STATE_length) +
|
|
GENX(BLEND_STATE_ENTRY_length) * surface_count;
|
|
|
|
struct anv_state blend_states =
|
|
anv_cmd_buffer_merge_dynamic(cmd_buffer, blend_dws,
|
|
pipeline->gfx7.blend_state, num_dwords, 64);
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) {
|
|
bsp.BlendStatePointer = blend_states.offset;
|
|
}
|
|
}
|
|
|
|
cmd_buffer->state.gfx.dirty = 0;
|
|
}
|
|
|
|
void
|
|
genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
|
|
bool enable)
|
|
{
|
|
/* The NP PMA fix doesn't exist on gfx7 */
|
|
}
|