mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-22 13:30:12 +01:00
6341b3cd87
Borderlands 3 (both DX11 and DX12 renderers) have a common pattern across many shaders: con 32x4 %510 = (uint32)txf %2 (handle), %1191 (0x10) (coord), %1 (0x0) (lod), 0 (texture) con 32x4 %512 = (uint32)txf %2 (handle), %1511 (0x11) (coord), %1 (0x0) (lod), 0 (texture) ... con 32x4 %550 = (uint32)txf %2 (handle), %1549 (0x25) (coord), %1 (0x0) (lod), 0 (texture) con 32x4 %552 = (uint32)txf %2 (handle), %1551 (0x26) (coord), %1 (0x0) (lod), 0 (texture) A single basic block contains piles of texelFetches from a 1D buffer texture, with constant coordinates. In most cases, only the .x channel of the result is read. So we have something on the order of 28 sampler messages, each asking for...a single uint32_t scalar value. Because our sampler doesn't have any support for convergent block loads (like the untyped LSC transpose messages for SSBOs)...this means we were emitting SIMD8/16 (or SIMD16/32 on Xe2) sampler messages for every single scalar, replicating what's effectively a SIMD1 value to the entire register. This is hugely wasteful, both in terms of register pressure, and also in back-and-forth sending and receiving memory messages. The good news is we can take advantage of our explicit SIMD model to handle this more efficiently. This patch adds a new optimization pass that detects a series of SHADER_OPCODE_TXF_LOGICAL, in the same basic block, with constant offsets, from the same texture. It constructs a new divergent coordinate where each channel is one of the constants (i.e <10, 11, 12, ..., 26> in the above example). It issues a new NoMask divergent texel fetch which loads N useful channels in one go, and replaces the rest with expansion MOVs that splat the SIMD1 result back to the full SIMD width. (These get copy propagated away.) We can pick the SIMD size of the load independently of the native shader width as well. On Xe2, those 28 convergent loads become a single SIMD32 ld message. On earlier hardware, we use 2 SIMD16 messages. Or we can use a smaller size when there aren't many to combine. In fossil-db, this cuts 27% of send messages in affected shaders, 3-6% of cycles, 2-3% of instructions, and 8-12% of live registers. On A770, this improves performance of Borderlands 3 by roughly 2.5-3.5%. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32573>
319 lines
8.4 KiB
Meson
319 lines
8.4 KiB
Meson
# Copyright © 2017 Intel Corporation
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# SPDX-License-Identifier: MIT
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intel_nir_files = files(
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'intel_nir.h',
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'intel_nir.c',
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'intel_nir_blockify_uniform_loads.c',
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'intel_nir_clamp_image_1d_2d_array_sizes.c',
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'intel_nir_clamp_per_vertex_loads.c',
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'intel_nir_lower_conversions.c',
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'intel_nir_lower_non_uniform_barycentric_at_sample.c',
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'intel_nir_lower_non_uniform_resource_intel.c',
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'intel_nir_lower_printf.c',
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'intel_nir_lower_shading_rate_output.c',
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'intel_nir_lower_sparse.c',
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'intel_nir_lower_texture.c',
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'intel_nir_opt_peephole_ffma.c',
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'intel_nir_opt_peephole_imul32x16.c',
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'intel_nir_tcs_workarounds.c',
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)
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libintel_compiler_brw_files = files(
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'brw_cfg.cpp',
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'brw_cfg.h',
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'brw_compile_bs.cpp',
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'brw_compile_cs.cpp',
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'brw_compile_fs.cpp',
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'brw_compile_gs.cpp',
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'brw_compile_mesh.cpp',
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'brw_compile_tcs.cpp',
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'brw_compile_tes.cpp',
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'brw_compile_vs.cpp',
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'brw_compiler.c',
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'brw_compiler.h',
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'brw_debug_recompile.c',
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'brw_def_analysis.cpp',
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'brw_disasm.c',
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'brw_disasm_info.cpp',
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'brw_disasm_info.h',
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'brw_eu.c',
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'brw_eu_compact.c',
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'brw_eu_defines.h',
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'brw_eu_emit.c',
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'brw_eu.h',
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'brw_eu_validate.c',
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'brw_fs_bank_conflicts.cpp',
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'brw_fs_builder.h',
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'brw_fs_cmod_propagation.cpp',
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'brw_fs_combine_constants.cpp',
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'brw_fs_copy_propagation.cpp',
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'brw_fs.cpp',
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'brw_fs_cse.cpp',
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'brw_fs_dead_code_eliminate.cpp',
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'brw_fs_generator.cpp',
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'brw_fs.h',
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'brw_fs_live_variables.cpp',
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'brw_fs_live_variables.h',
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'brw_fs_lower.cpp',
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'brw_fs_lower_dpas.cpp',
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'brw_fs_lower_integer_multiplication.cpp',
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'brw_fs_lower_pack.cpp',
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'brw_fs_lower_regioning.cpp',
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'brw_fs_lower_simd_width.cpp',
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'brw_fs_nir.cpp',
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'brw_fs_opt.cpp',
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'brw_fs_opt_algebraic.cpp',
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'brw_fs_opt_virtual_grfs.cpp',
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'brw_fs_reg_allocate.cpp',
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'brw_fs_register_coalesce.cpp',
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'brw_fs_saturate_propagation.cpp',
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'brw_fs_scoreboard.cpp',
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'brw_fs_thread_payload.cpp',
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'brw_fs_validate.cpp',
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'brw_fs_visitor.cpp',
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'brw_fs_workaround.cpp',
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'brw_inst.h',
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'brw_ir.h',
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'brw_ir_allocator.h',
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'brw_ir_analysis.h',
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'brw_ir_fs.h',
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'brw_ir_performance.h',
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'brw_ir_performance.cpp',
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'brw_isa_info.h',
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'brw_lower_logical_sends.cpp',
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'brw_lower_subgroup_ops.cpp',
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'brw_nir.h',
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'brw_nir.c',
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'brw_nir_analyze_ubo_ranges.c',
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'brw_nir_lower_cooperative_matrix.c',
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'brw_nir_lower_cs_intrinsics.c',
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'brw_nir_lower_alpha_to_coverage.c',
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'brw_nir_lower_intersection_shader.c',
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'brw_nir_lower_ray_queries.c',
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'brw_nir_lower_rt_intrinsics.c',
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'brw_nir_lower_shader_calls.c',
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'brw_nir_lower_storage_image.c',
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'brw_nir_opt_fsat.c',
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'brw_nir_rt.h',
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'brw_nir_rt.c',
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'brw_nir_rt_builder.h',
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'brw_opt_txf_combiner.cpp',
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'brw_packed_float.c',
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'brw_print.cpp',
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'brw_prim.h',
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'brw_private.h',
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'brw_reg.h',
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'brw_reg_type.c',
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'brw_reg_type.h',
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'brw_rt.h',
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'brw_schedule_instructions.cpp',
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'brw_shader.cpp',
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'brw_simd_selection.cpp',
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'brw_vue_map.c',
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)
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brw_device_sha1_gen_src = custom_target('brw_device_sha1_gen.c',
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input : ['brw_device_sha1_gen_c.py', '../dev/intel_device_info.py'],
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output : ['brw_device_sha1_gen.c'],
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command : [prog_python, '@INPUT0@', '--outdir', meson.current_build_dir()])
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brw_nir_lower_fsign = custom_target(
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'brw_nir_lower_fsign.c',
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input : 'brw_nir_lower_fsign.py',
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output : 'brw_nir_lower_fsign.c',
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command : [
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prog_python, '@INPUT@', '-p', dir_compiler_nir,
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],
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depend_files : nir_algebraic_depends,
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capture : true,
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)
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brw_nir_trig = custom_target(
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'brw_nir_trig_workarounds.c',
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input : 'brw_nir_trig_workarounds.py',
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output : 'brw_nir_trig_workarounds.c',
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command : [
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prog_python, '@INPUT@', '-p', dir_compiler_nir,
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],
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depend_files : nir_algebraic_depends,
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capture : true,
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)
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libintel_compiler_brw = static_library(
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'intel_compiler',
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[libintel_compiler_brw_files, intel_nir_files, brw_nir_lower_fsign, brw_nir_trig, ir_expression_operation_h, [brw_device_sha1_gen_src]],
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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dependencies : [idep_nir_headers, idep_mesautil, idep_intel_dev],
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build_by_default : false,
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)
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idep_intel_compiler_brw = declare_dependency(
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link_with : [libintel_compiler_brw],
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dependencies : [
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idep_nir,
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idep_mesautil,
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],
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)
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# For now this tool is only going to be used by Anv
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if get_option('intel-clc') == 'system'
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prog_intel_clc = find_program('intel_clc', native : true)
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dep_prog_intel_clc = []
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elif with_intel_clc
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prog_intel_clc = executable(
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'intel_clc',
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[
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'intel_clc.c',
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'brw_kernel.c',
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# Use just the nir_options part of ELK instead of fully linking.
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'elk/elk_nir_options.h',
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'elk/elk_nir_options.c',
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],
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link_with : [libisl],
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [pre_args, no_override_init_args],
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link_args : [ld_args_build_id],
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dependencies : [idep_nir, idep_vtn, idep_mesaclc, idep_mesautil, idep_intel_dev,
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idep_intel_compiler_brw],
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# If we can run host binaries directly, just build intel_clc for the host.
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# Most commonly this happens when doing a cross compile from an x86_64 build
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# machine to an x86 host
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native : not meson.can_run_host_binaries(),
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install : get_option('install-intel-clc'),
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)
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dep_prog_intel_clc = [prog_intel_clc]
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endif
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if with_tests
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test(
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'intel_compiler_brw_tests',
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executable(
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'intel_compiler_brw_tests',
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files(
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'test_eu_compact.cpp',
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'test_eu_validate.cpp',
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'test_fs_cmod_propagation.cpp',
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'test_fs_combine_constants.cpp',
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'test_fs_copy_propagation.cpp',
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'test_fs_cse.cpp',
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'test_fs_saturate_propagation.cpp',
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'test_fs_scoreboard.cpp',
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'test_simd_selection.cpp',
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'test_vf_float_conversions.cpp',
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),
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ir_expression_operation_h,
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include_directories : [inc_include, inc_src, inc_intel],
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link_with : libisl,
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dependencies : [idep_gtest, idep_nir, idep_mesautil, idep_intel_dev,
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idep_intel_compiler_brw],
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),
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suite : ['intel'],
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protocol : 'gtest',
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)
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endif
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if with_intel_tools
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bison_command = []
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if yacc_is_bison
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bison_command = [
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prog_bison, '@INPUT@', '--defines=@OUTPUT1@',
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'--output=@OUTPUT0@'
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]
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else
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bison_command = [
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prog_bison, '-H', '@OUTPUT1@',
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'-o', '@OUTPUT0@', '@INPUT@'
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]
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endif
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brw_gram_tab = custom_target(
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'brw_gram.tab.[ch]',
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input : 'brw_gram.y',
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output : ['brw_gram.tab.c', 'brw_gram.tab.h'],
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command : bison_command
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)
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brw_lex_yy_c = custom_target(
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'brw_lex.yy.c',
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input : 'brw_lex.l',
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output : 'brw_lex.yy.c',
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command : [prog_flex, '-o', '@OUTPUT@', '@INPUT@']
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)
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brw_asm_deps = [
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dep_thread,
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idep_intel_compiler_brw,
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idep_intel_dev,
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idep_mesautil,
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]
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brw_asm = static_library(
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'brw_asm',
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['brw_asm.c', brw_gram_tab[0], brw_gram_tab[1], brw_lex_yy_c],
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dependencies : brw_asm_deps,
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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build_by_default : false,
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)
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idep_brw_asm = declare_dependency(
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link_with : brw_asm,
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dependencies : brw_asm_deps,
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)
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brw_asm_tool = executable(
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'brw_asm',
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['brw_asm_tool.c'],
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dependencies : idep_brw_asm,
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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install : true
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)
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asm_testcases = [
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['skl', 'gfx9'],
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['icl', 'gfx11'],
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['tgl', 'gfx12'],
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['dg2', 'gfx12.5'],
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]
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test_runner = find_program('tests/run-test.py')
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foreach testcase : asm_testcases
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_gen_name = testcase[0]
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_gen_num = testcase[1]
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_gen_folder = join_paths(meson.current_source_dir(), 'tests',
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_gen_num.replace('gfx', 'gen'))
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test(
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'brw_asm_' + _gen_num, test_runner,
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args : [
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'--brw_asm', brw_asm_tool,
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'--gen_name', _gen_name,
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'--gen_folder', _gen_folder,
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],
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suite : 'intel',
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)
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endforeach
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brw_disasm_tool = executable(
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'brw_disasm',
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files('brw_disasm_tool.c'),
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dependencies : [idep_mesautil, dep_thread, idep_intel_dev,
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idep_intel_compiler_brw],
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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install : true
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)
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endif
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subdir('elk')
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