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13b25a6114
The hardware doesn't extend in this case, we need to extend for it. This fixes 32-bit render target formats with lower_mediump_io. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21082>
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* Copyright 2022 Alyssa Rosenzweig
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* SPDX-License-Identifier: MIT
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*/
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#include "agx_nir_format_helpers.h"
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#include "agx_tilebuffer.h"
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#include "nir.h"
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#include "nir_builder.h"
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#define ALL_SAMPLES 0xFF
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static bool
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tib_filter(const nir_instr *instr, UNUSED const void *_)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output &&
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intr->intrinsic != nir_intrinsic_load_output)
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return false;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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assert(sem.dual_source_blend_index == 0 && "todo: dual source blending");
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return (sem.location >= FRAG_RESULT_DATA0);
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}
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static nir_ssa_def *
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tib_impl(nir_builder *b, nir_instr *instr, void *data)
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{
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struct agx_tilebuffer_layout *tib = data;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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unsigned rt = sem.location - FRAG_RESULT_DATA0;
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assert(rt < ARRAY_SIZE(tib->logical_format));
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enum pipe_format logical_format = tib->logical_format[rt];
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enum pipe_format format = agx_tilebuffer_physical_format(tib, rt);
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unsigned comps = util_format_get_nr_components(logical_format);
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if (intr->intrinsic == nir_intrinsic_store_output) {
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/* Delete stores to nonexistant render targets */
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if (logical_format == PIPE_FORMAT_NONE)
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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nir_ssa_def *value = intr->src[0].ssa;
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/* Trim to format as required by hardware */
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value = nir_trim_vector(b, intr->src[0].ssa, comps);
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/* The hardware cannot extend for a 32-bit format. Extend ourselves. */
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if (format == PIPE_FORMAT_R32_UINT && value->bit_size == 16) {
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if (util_format_is_pure_sint(logical_format))
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value = nir_i2i32(b, value);
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else if (util_format_is_pure_uint(logical_format))
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value = nir_u2u32(b, value);
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else
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value = nir_f2f32(b, value);
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}
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nir_store_local_pixel_agx(
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b, value, nir_imm_intN_t(b, ALL_SAMPLES, 16),
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.base = tib->offset_B[rt],
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.write_mask = nir_intrinsic_write_mask(intr) & BITFIELD_MASK(comps),
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.format = format);
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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} else {
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uint8_t bit_size = nir_dest_bit_size(intr->dest);
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/* Loads from non-existant render targets are undefined in NIR but not
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* possible to encode in the hardware, delete them.
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*/
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if (logical_format == PIPE_FORMAT_NONE)
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return nir_ssa_undef(b, intr->num_components, bit_size);
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bool f16 = (format == PIPE_FORMAT_R16_FLOAT);
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/* Don't load with F16 */
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if (f16)
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format = PIPE_FORMAT_R16_UINT;
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nir_ssa_def *res = nir_load_local_pixel_agx(
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b, MIN2(intr->num_components, comps), f16 ? 16 : bit_size,
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nir_imm_intN_t(b, ALL_SAMPLES, 16), .base = tib->offset_B[rt],
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.format = format);
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/* Extend floats */
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if (f16 && nir_dest_bit_size(intr->dest) != 16) {
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assert(nir_dest_bit_size(intr->dest) == 32);
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res = nir_f2f32(b, res);
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}
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res = nir_sign_extend_if_sint(b, res, logical_format);
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res = nir_pad_vector(b, res, intr->num_components);
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return res;
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}
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}
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bool
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agx_nir_lower_tilebuffer(nir_shader *shader, struct agx_tilebuffer_layout *tib)
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{
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assert(shader->info.stage == MESA_SHADER_FRAGMENT);
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return nir_shader_lower_instructions(shader, tib_filter, tib_impl, tib);
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}
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