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16f66ffe55
In ray tracing dispatch, we have dispatch.threads set to 0 since we
calculate the local_size_x/y/z based on the launch sizes.
This change takes 0 threads into an account and returh the TG size 8 in
such scenarios. Before this change, we were setting TG size to 2.
Fixes: 0c4e1c9efc ("intel/common: Add helper for compute thread group dispatch size")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38229>
237 lines
7.2 KiB
C
237 lines
7.2 KiB
C
/*
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* Copyright 2024 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include <stdlib.h>
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#include "dev/intel_debug.h"
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#include "intel_common.h"
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#include "intel_engine.h"
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#include "util/compiler.h"
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/* Updates intel_device_info fields that has dependencies on intel/common
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* functions.
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*/
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void intel_common_update_device_info(int fd, struct intel_device_info *devinfo)
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{
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struct intel_query_engine_info *engine_info;
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enum intel_engine_class klass;
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engine_info = intel_engine_get_info(fd, devinfo->kmd_type);
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if (!engine_info)
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return;
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devinfo->has_compute_engine = intel_engines_count(engine_info,
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INTEL_ENGINE_CLASS_COMPUTE);
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for (klass = 0; klass < INTEL_ENGINE_CLASS_INVALID; klass++)
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devinfo->engine_class_supported_count[klass] =
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intel_engines_supported_count(fd, devinfo, engine_info, klass);
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free(engine_info);
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}
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void
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intel_compute_engine_async_threads_limit(const struct intel_device_info *devinfo,
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uint32_t hw_threads_in_wg,
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bool slm_or_barrier_enabled,
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uint8_t *ret_pixel_async_compute_thread_limit,
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uint8_t *ret_z_pass_async_compute_thread_limit,
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uint8_t *ret_np_z_async_throttle_settings)
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{
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/* Spec recommended SW values.
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* IMPORTANT: values set to this variables are HW values
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*/
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uint8_t pixel_async_compute_thread_limit = 2;
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uint8_t z_pass_async_compute_thread_limit = 0;
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uint8_t np_z_async_throttle_settings = 0;
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bool has_vrt = devinfo->verx10 >= 300 && !INTEL_DEBUG(DEBUG_NO_VRT);
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/* When VRT is enabled async threads limits don't have effect */
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if (!slm_or_barrier_enabled || has_vrt) {
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*ret_pixel_async_compute_thread_limit = pixel_async_compute_thread_limit;
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*ret_z_pass_async_compute_thread_limit = z_pass_async_compute_thread_limit;
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*ret_np_z_async_throttle_settings = np_z_async_throttle_settings;
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return;
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}
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if (devinfo->verx10 >= 200) {
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/* Spec give us a table with Throttle value | SIMD | MAX API threads(LWS).
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* HW threads = MAX API threads(LWS) / SIMD
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*/
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switch (hw_threads_in_wg) {
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case 0 ... 2:
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/* Minimum is Max 2 but lets use spec recommended value below */
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FALLTHROUGH;
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case 3 ... 8:
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/* Max 8 */
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pixel_async_compute_thread_limit = 2;
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break;
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case 9 ... 16:
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/* Max 16 */
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pixel_async_compute_thread_limit = 3;
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break;
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case 17 ... 24:
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/* Max 24 */
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pixel_async_compute_thread_limit = 4;
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break;
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case 25 ... 32:
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/* Max 32 */
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pixel_async_compute_thread_limit = 5;
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break;
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case 33 ... 40:
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/* Max 40 */
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pixel_async_compute_thread_limit = 6;
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break;
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case 41 ... 48:
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/* Max 48 */
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pixel_async_compute_thread_limit = 7;
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break;
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default:
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/* No limit applied */
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pixel_async_compute_thread_limit = 0;
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}
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switch (hw_threads_in_wg) {
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case 0 ... 32:
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/* Minimum is Max 32 but lets use spec recommended value below */
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FALLTHROUGH;
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case 33 ... 40:
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/* Minimum is Max 40 but lets use spec recommended value below */
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FALLTHROUGH;
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case 41 ... 48:
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/* Minimum is Max 48 but lets use spec recommended value below */
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FALLTHROUGH;
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case 49 ... 56:
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/* Minimum is Max 56 but lets use spec recommended value below */
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FALLTHROUGH;
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case 57 ... 60:
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/* Max 60 */
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z_pass_async_compute_thread_limit = 0;
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break;
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default:
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/* No limit applied */
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z_pass_async_compute_thread_limit = 1;
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}
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switch (hw_threads_in_wg) {
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case 0 ... 32:
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/* Max 32 */
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np_z_async_throttle_settings = 1;
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break;
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case 33 ... 40:
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/* Max 40 */
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np_z_async_throttle_settings = 2;
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break;
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case 41 ... 48:
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/* Max 48 */
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np_z_async_throttle_settings = 3;
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break;
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default:
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/* Use the same settings as the Pixel shader Async compute setting,
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* for values >= async compute settings disables the limits
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*/
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np_z_async_throttle_settings = 0;
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}
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} else {
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switch (hw_threads_in_wg) {
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case 0 ... 4:
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/* Minimum is Max 2 but lets use spec recommended value below */
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FALLTHROUGH;
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case 5 ... 16:
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/* Max 8 */
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pixel_async_compute_thread_limit = 2;
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break;
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case 17 ... 32:
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/* Max 16 */
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pixel_async_compute_thread_limit = 3;
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break;
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case 33 ... 48:
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/* Max 24 */
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pixel_async_compute_thread_limit = 4;
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break;
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case 49 ... 64:
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/* Max 32 */
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pixel_async_compute_thread_limit = 5;
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break;
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case 65 ... 80:
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/* Max 40 */
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pixel_async_compute_thread_limit = 6;
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break;
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case 81 ... 96:
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/* Max 48 */
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pixel_async_compute_thread_limit = 7;
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break;
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default:
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/* No limit applied */
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pixel_async_compute_thread_limit = 0;
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}
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switch (hw_threads_in_wg) {
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case 0 ... 64:
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/* Minimum is Max 32 but lets use spec recommended value below */
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FALLTHROUGH;
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case 65 ... 80:
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/* Minimum is Max 40 but lets use spec recommended value below */
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FALLTHROUGH;
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case 81 ... 96:
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/* Minimum is Max 48 but lets use spec recommended value below */
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FALLTHROUGH;
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case 97 ... 112:
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/* Minimum is Max 56 but lets use spec recommended value below */
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FALLTHROUGH;
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case 113 ... 120:
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/* Max 60 */
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z_pass_async_compute_thread_limit = 0;
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break;
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default:
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/* Max 64/No limit applied */
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z_pass_async_compute_thread_limit = 1;
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}
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switch (hw_threads_in_wg) {
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case 0 ... 64:
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/* Max 32 */
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np_z_async_throttle_settings = 1;
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break;
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case 65 ... 80:
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/* Max 40 */
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np_z_async_throttle_settings = 2;
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break;
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case 81 ... 96:
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/* Max 48 */
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np_z_async_throttle_settings = 3;
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break;
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default:
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/* Use the same settings as the Pixel shader Async compute setting,
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* for values >= async compute settings disables the limits
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*/
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np_z_async_throttle_settings = 0;
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}
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}
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assert(np_z_async_throttle_settings != 0 || pixel_async_compute_thread_limit == 0);
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*ret_pixel_async_compute_thread_limit = pixel_async_compute_thread_limit;
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*ret_z_pass_async_compute_thread_limit = z_pass_async_compute_thread_limit;
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*ret_np_z_async_throttle_settings = np_z_async_throttle_settings;
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}
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int
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intel_compute_threads_group_dispatch_size(uint32_t hw_threads_in_wg)
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{
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/* Following value calculated based on overdispatch is disabled. In case if
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* compute overdispatch disabled set to 1, then we need to use TG Size 1.
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*/
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switch (hw_threads_in_wg) {
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case 0 ... 16:
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return 0;
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case 17 ... 32:
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return 1;
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default:
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return 2;
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}
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}
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