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73cbb35442
This keeps the directory structure a bit more organized: - brw specific code - elk specific code - common NIR passes that could be used in both places It also means that you can now 'git grep' in the brw directory without finding a bunch of elk code, or having to "grep thing b*". Reviewed-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37755>
151 lines
4.2 KiB
C++
151 lines
4.2 KiB
C++
/*
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* Copyright © 2025 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "test_helpers.h"
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#include "brw_builder.h"
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class insert_load_reg_test : public brw_shader_pass_test {};
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TEST_F(insert_load_reg_test, basic)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_builder exp = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst = vgrf(bld, exp, BRW_TYPE_F);
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brw_reg src = vgrf(bld, exp, BRW_TYPE_F);
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bld.ADD(dst, src, brw_imm_f(1.0));
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EXPECT_PROGRESS(brw_insert_load_reg, bld);
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exp.ADD(dst, exp.LOAD_REG(src), brw_imm_f(1.0));
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EXPECT_SHADERS_MATCH(bld, exp);
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}
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TEST_F(insert_load_reg_test, already_defs)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst0 = vgrf(bld, BRW_TYPE_F);
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brw_reg dst1 = vgrf(bld, BRW_TYPE_F);
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brw_reg src0 = retype(brw_vec16_reg(FIXED_GRF, 2, 0), BRW_TYPE_F);
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/* The first ADD will produce a def due its FIXED_GRF and IMM sources. The
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* second ADD will also produces a def due to its def and IMM
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* sources. brw_insert_load_reg shouldn't do anything.
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*/
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bld.ADD(dst0, src0, brw_imm_f(1.0));
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bld.ADD(dst1, dst0, brw_imm_f(1.0));
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EXPECT_NO_PROGRESS(brw_insert_load_reg, bld);
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}
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TEST_F(insert_load_reg_test, stride_0)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst = vgrf(bld, BRW_TYPE_F);
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brw_reg src = component(vgrf(bld, BRW_TYPE_F), 0);
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ASSERT_EQ(src.stride, 0);
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bld.ADD(dst, src, brw_imm_f(1.0));
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EXPECT_NO_PROGRESS(brw_insert_load_reg, bld);
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}
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TEST_F(insert_load_reg_test, stride_2)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst = vgrf(bld, BRW_TYPE_D);
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brw_reg src = subscript(vgrf(bld, BRW_TYPE_D), BRW_TYPE_W, 0);
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ASSERT_EQ(src.stride, 2);
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bld.ADD(dst, src, brw_imm_d(1));
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EXPECT_NO_PROGRESS(brw_insert_load_reg, bld);
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}
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TEST_F(insert_load_reg_test, is_scalar)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_builder xbld = bld.scalar_group();
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brw_reg dst = vgrf(bld, BRW_TYPE_F);
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brw_reg src = vgrf(xbld, BRW_TYPE_F);
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/* Currently, is_scalar cases are treated the same as other stride=0
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* cases. This does not need to be the case, and it may (should!) be
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* changed in the future. Split this out as a separate test.
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*/
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src.is_scalar = true;
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bld.ADD(dst, component(src, 0), brw_imm_f(1.0));
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EXPECT_NO_PROGRESS(brw_insert_load_reg, bld);
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}
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TEST_F(insert_load_reg_test, emit_load_reg_once)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_builder exp = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst0 = vgrf(bld, exp, BRW_TYPE_F);
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brw_reg dst1 = vgrf(bld, exp, BRW_TYPE_F);
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brw_reg src = vgrf(bld, exp, BRW_TYPE_F);
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/* Since both instructions use the same source, only one LOAD_REG should be
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* generated.
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*/
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bld.ADD(dst0, src, brw_imm_f(1.0));
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bld.ADD(dst1, src, brw_imm_f(2.0));
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EXPECT_PROGRESS(brw_insert_load_reg, bld);
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brw_reg dst2 = exp.LOAD_REG(src);
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exp.ADD(dst0, dst2, brw_imm_f(1.0));
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exp.ADD(dst1, dst2, brw_imm_f(2.0));
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EXPECT_SHADERS_MATCH(bld, exp);
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}
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TEST_F(insert_load_reg_test, no_mask)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_builder exp = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst0 = vgrf(bld, exp, BRW_TYPE_F);
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brw_reg dst1 = vgrf(bld, exp, BRW_TYPE_F);
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brw_reg src0 = vgrf(bld, exp, BRW_TYPE_F);
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bld.ADD(dst0, src0, brw_imm_f(1.0));
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bld.exec_all().ADD(dst1, src0, brw_imm_f(2.0));
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EXPECT_PROGRESS(brw_insert_load_reg, bld);
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brw_reg src1 = exp.LOAD_REG(src0);
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exp.ADD(dst0, src1, brw_imm_f(1.0));
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brw_reg src2 = exp.exec_all().LOAD_REG(src0);
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exp.exec_all().ADD(dst1, src2, brw_imm_f(2.0));
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EXPECT_SHADERS_MATCH(bld, exp);
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}
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TEST_F(insert_load_reg_test, odd_size)
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{
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brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
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brw_reg dst = vgrf(bld, BRW_TYPE_D);
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brw_reg src = vgrf(bld, BRW_TYPE_D, 3, 8);
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/* The register allocation size is 3 SIMD8 units. Since that is not an even
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* multiple of the exec size, it would be very difficult to generate a
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* correct LOAD_REG. This should be skipped.
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*/
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bld.ADD(dst, src, brw_imm_d(1));
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EXPECT_NO_PROGRESS(brw_insert_load_reg, bld);
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}
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