mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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f9c948ed00
Version 0.170.2 removes most of the error enums. In many cases, I had to replace an error with a less accurate (or even incorrect) one. In other cases, the error path is replaced with an assertion.
571 lines
26 KiB
C
571 lines
26 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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static void
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gen7_emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info)
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{
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const bool sgvs = pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid;
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const uint32_t element_count = info->attributeCount + (sgvs ? 1 : 0);
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const uint32_t num_dwords = 1 + element_count * 2;
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uint32_t *p;
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if (info->attributeCount > 0) {
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p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GEN7_3DSTATE_VERTEX_ELEMENTS);
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}
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for (uint32_t i = 0; i < info->attributeCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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const struct anv_format *format = anv_format_for_vk_format(desc->format);
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format->surface_format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offsetInBytes,
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.Component0Control = VFCOMP_STORE_SRC,
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.Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
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.Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + i * 2], &element);
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}
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if (sgvs) {
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.Valid = true,
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/* FIXME: Do we need to provide the base vertex as component 0 here
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* to support the correct base vertex ID? */
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.Component0Control = VFCOMP_STORE_0,
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.Component1Control = VFCOMP_STORE_0,
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.Component2Control = VFCOMP_STORE_VID,
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.Component3Control = VFCOMP_STORE_IID
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->attributeCount * 2], &element);
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}
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}
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static const uint32_t vk_to_gen_cullmode[] = {
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[VK_CULL_MODE_NONE] = CULLMODE_NONE,
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[VK_CULL_MODE_FRONT] = CULLMODE_FRONT,
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[VK_CULL_MODE_BACK] = CULLMODE_BACK,
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[VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH
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};
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static const uint32_t vk_to_gen_fillmode[] = {
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[VK_FILL_MODE_POINTS] = RASTER_POINT,
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[VK_FILL_MODE_WIREFRAME] = RASTER_WIREFRAME,
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[VK_FILL_MODE_SOLID] = RASTER_SOLID
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};
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static const uint32_t vk_to_gen_front_face[] = {
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[VK_FRONT_FACE_CCW] = CounterClockwise,
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[VK_FRONT_FACE_CW] = Clockwise
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};
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static void
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gen7_emit_rs_state(struct anv_pipeline *pipeline,
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const VkPipelineRasterStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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struct GEN7_3DSTATE_SF sf = {
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GEN7_3DSTATE_SF_header,
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/* FIXME: Get this from pass info */
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.DepthBufferSurfaceFormat = D24_UNORM_X8_UINT,
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/* LegacyGlobalDepthBiasEnable */
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.StatisticsEnable = true,
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.FrontFaceFillMode = vk_to_gen_fillmode[info->fillMode],
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.BackFaceFillMode = vk_to_gen_fillmode[info->fillMode],
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.ViewTransformEnable = !(extra && extra->disable_viewport),
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.FrontWinding = vk_to_gen_front_face[info->frontFace],
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/* bool AntiAliasingEnable; */
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.CullMode = vk_to_gen_cullmode[info->cullMode],
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/* uint32_t LineEndCapAntialiasingRegionWidth; */
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.ScissorRectangleEnable = !(extra && extra->disable_scissor),
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/* uint32_t MultisampleRasterizationMode; */
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/* bool LastPixelEnable; */
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.TriangleStripListProvokingVertexSelect = 0,
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.LineStripListProvokingVertexSelect = 0,
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.TriangleFanProvokingVertexSelect = 0,
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/* uint32_t AALineDistanceMode; */
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/* uint32_t VertexSubPixelPrecisionSelect; */
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.UsePointWidthState = !pipeline->writes_point_size,
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.PointWidth = 1.0,
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};
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GEN7_3DSTATE_SF_pack(NULL, &pipeline->gen7.sf, &sf);
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}
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static const uint32_t vk_to_gen_compare_op[] = {
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[VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER,
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[VK_COMPARE_OP_LESS] = PREFILTEROPLESS,
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[VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL,
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[VK_COMPARE_OP_LESS_EQUAL] = PREFILTEROPLEQUAL,
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[VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER,
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[VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL,
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[VK_COMPARE_OP_GREATER_EQUAL] = PREFILTEROPGEQUAL,
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[VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS,
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};
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static const uint32_t vk_to_gen_stencil_op[] = {
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[VK_STENCIL_OP_KEEP] = STENCILOP_KEEP,
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[VK_STENCIL_OP_ZERO] = STENCILOP_ZERO,
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[VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE,
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[VK_STENCIL_OP_INC_CLAMP] = STENCILOP_INCRSAT,
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[VK_STENCIL_OP_DEC_CLAMP] = STENCILOP_DECRSAT,
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[VK_STENCIL_OP_INVERT] = STENCILOP_INVERT,
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[VK_STENCIL_OP_INC_WRAP] = STENCILOP_INCR,
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[VK_STENCIL_OP_DEC_WRAP] = STENCILOP_DECR,
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};
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static const uint32_t vk_to_gen_blend_op[] = {
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[VK_BLEND_OP_ADD] = BLENDFUNCTION_ADD,
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[VK_BLEND_OP_SUBTRACT] = BLENDFUNCTION_SUBTRACT,
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[VK_BLEND_OP_REVERSE_SUBTRACT] = BLENDFUNCTION_REVERSE_SUBTRACT,
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[VK_BLEND_OP_MIN] = BLENDFUNCTION_MIN,
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[VK_BLEND_OP_MAX] = BLENDFUNCTION_MAX,
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};
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static const uint32_t vk_to_gen_logic_op[] = {
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[VK_LOGIC_OP_COPY] = LOGICOP_COPY,
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[VK_LOGIC_OP_CLEAR] = LOGICOP_CLEAR,
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[VK_LOGIC_OP_AND] = LOGICOP_AND,
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[VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE,
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[VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED,
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[VK_LOGIC_OP_NOOP] = LOGICOP_NOOP,
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[VK_LOGIC_OP_XOR] = LOGICOP_XOR,
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[VK_LOGIC_OP_OR] = LOGICOP_OR,
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[VK_LOGIC_OP_NOR] = LOGICOP_NOR,
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[VK_LOGIC_OP_EQUIV] = LOGICOP_EQUIV,
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[VK_LOGIC_OP_INVERT] = LOGICOP_INVERT,
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[VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE,
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[VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED,
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[VK_LOGIC_OP_OR_INVERTED] = LOGICOP_OR_INVERTED,
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[VK_LOGIC_OP_NAND] = LOGICOP_NAND,
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[VK_LOGIC_OP_SET] = LOGICOP_SET,
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};
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static const uint32_t vk_to_gen_blend[] = {
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[VK_BLEND_ZERO] = BLENDFACTOR_ZERO,
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[VK_BLEND_ONE] = BLENDFACTOR_ONE,
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[VK_BLEND_SRC_COLOR] = BLENDFACTOR_SRC_COLOR,
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[VK_BLEND_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR,
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[VK_BLEND_DEST_COLOR] = BLENDFACTOR_DST_COLOR,
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[VK_BLEND_ONE_MINUS_DEST_COLOR] = BLENDFACTOR_INV_DST_COLOR,
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[VK_BLEND_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA,
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[VK_BLEND_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA,
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[VK_BLEND_DEST_ALPHA] = BLENDFACTOR_DST_ALPHA,
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[VK_BLEND_ONE_MINUS_DEST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA,
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[VK_BLEND_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR,
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[VK_BLEND_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR,
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[VK_BLEND_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA,
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[VK_BLEND_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA,
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[VK_BLEND_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE,
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[VK_BLEND_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR,
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[VK_BLEND_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR,
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[VK_BLEND_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA,
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[VK_BLEND_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA,
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};
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static void
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gen7_emit_ds_state(struct anv_pipeline *pipeline,
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const VkPipelineDepthStencilStateCreateInfo *info)
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{
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if (info == NULL) {
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/* We're going to OR this together with the dynamic state. We need
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* to make sure it's initialized to something useful.
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*/
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memset(pipeline->gen7.depth_stencil_state, 0,
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sizeof(pipeline->gen7.depth_stencil_state));
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return;
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}
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bool has_stencil = false; /* enable if subpass has stencil? */
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struct GEN7_DEPTH_STENCIL_STATE state = {
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/* Is this what we need to do? */
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.StencilBufferWriteEnable = has_stencil,
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.StencilTestEnable = info->stencilTestEnable,
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.StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp],
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.StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp],
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.StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp],
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.StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp],
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.DoubleSidedStencilEnable = true,
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.BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp],
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.BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp],
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.BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp],
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.BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp],
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.DepthTestEnable = info->depthTestEnable,
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.DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp],
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.DepthBufferWriteEnable = info->depthWriteEnable,
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};
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GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state);
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}
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static void
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gen7_emit_cb_state(struct anv_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *info)
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{
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struct anv_device *device = pipeline->device;
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/* FIXME-GEN7: All render targets share blend state settings on gen7, we
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* can't implement this.
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*/
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const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0];
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uint32_t num_dwords = GEN7_BLEND_STATE_length;
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pipeline->blend_state =
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anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64);
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struct GEN7_BLEND_STATE blend_state = {
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.ColorBufferBlendEnable = a->blendEnable,
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.IndependentAlphaBlendEnable = true, /* FIXME: yes? */
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.AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha],
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.SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha],
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.DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha],
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.ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor],
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.SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor],
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.DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor],
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.AlphaToCoverageEnable = info->alphaToCoverageEnable,
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#if 0
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bool AlphaToOneEnable;
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bool AlphaToCoverageDitherEnable;
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#endif
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.WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT),
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.WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT),
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.WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT),
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.WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT),
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.LogicOpEnable = info->logicOpEnable,
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.LogicOpFunction = vk_to_gen_logic_op[info->logicOp],
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#if 0
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bool AlphaTestEnable;
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uint32_t AlphaTestFunction;
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bool ColorDitherEnable;
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uint32_t XDitherOffset;
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uint32_t YDitherOffset;
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uint32_t ColorClampRange;
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bool PreBlendColorClampEnable;
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bool PostBlendColorClampEnable;
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#endif
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};
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GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS,
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.BlendStatePointer = pipeline->blend_state.offset);
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}
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static const uint32_t vk_to_gen_primitive_type[] = {
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[VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST,
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[VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST,
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[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN,
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[VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ] = _3DPRIM_LINELIST_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ] = _3DPRIM_LINESTRIP_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ] = _3DPRIM_TRILIST_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ] = _3DPRIM_TRISTRIP_ADJ,
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[VK_PRIMITIVE_TOPOLOGY_PATCH] = _3DPRIM_PATCHLIST_1
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};
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static inline uint32_t
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scratch_space(const struct brw_stage_prog_data *prog_data)
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{
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return ffs(prog_data->total_scratch / 1024);
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}
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VkResult
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gen7_graphics_pipeline_create(
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VkDevice _device,
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const VkGraphicsPipelineCreateInfo* pCreateInfo,
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const struct anv_graphics_pipeline_create_info *extra,
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VkPipeline* pPipeline)
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{
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ANV_FROM_HANDLE(anv_device, device, _device);
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struct anv_pipeline *pipeline;
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VkResult result;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
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pipeline = anv_device_alloc(device, sizeof(*pipeline), 8,
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VK_SYSTEM_ALLOC_TYPE_API_OBJECT);
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if (pipeline == NULL)
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return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
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result = anv_pipeline_init(pipeline, device, pCreateInfo, extra);
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if (result != VK_SUCCESS) {
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anv_device_free(device, pipeline);
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return result;
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}
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assert(pCreateInfo->pVertexInputState);
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gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState);
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assert(pCreateInfo->pRasterState);
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gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra);
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gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState);
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gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS,
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.StatisticsEnable = true);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_HS, .Enable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_TE, .TEEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
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.ConstantBufferOffset = 0,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
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.ConstantBufferOffset = 4,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
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.ConstantBufferOffset = 8,
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.ConstantBufferSize = 4);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS);
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const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState;
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP,
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.FrontWinding = vk_to_gen_front_face[rs_info->frontFace],
|
|
.CullMode = vk_to_gen_cullmode[rs_info->cullMode],
|
|
.ClipEnable = true,
|
|
.APIMode = APIMODE_OGL,
|
|
.ViewportXYClipTestEnable = !(extra && extra->disable_viewport),
|
|
.ClipMode = CLIPMODE_NORMAL,
|
|
.TriangleStripListProvokingVertexSelect = 0,
|
|
.LineStripListProvokingVertexSelect = 0,
|
|
.TriangleFanProvokingVertexSelect = 0,
|
|
.MinimumPointWidth = 0.125,
|
|
.MaximumPointWidth = 255.875);
|
|
|
|
uint32_t samples = 1;
|
|
uint32_t log2_samples = __builtin_ffs(samples) - 1;
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_MULTISAMPLE,
|
|
.PixelLocation = PIXLOC_CENTER,
|
|
.NumberofMultisamples = log2_samples);
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SAMPLE_MASK,
|
|
.SampleMask = 0xff);
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_VS,
|
|
.VSURBStartingAddress = pipeline->urb.vs_start,
|
|
.VSURBEntryAllocationSize = pipeline->urb.vs_size - 1,
|
|
.VSNumberofURBEntries = pipeline->urb.nr_vs_entries);
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_GS,
|
|
.GSURBStartingAddress = pipeline->urb.gs_start,
|
|
.GSURBEntryAllocationSize = pipeline->urb.gs_size - 1,
|
|
.GSNumberofURBEntries = pipeline->urb.nr_gs_entries);
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_HS,
|
|
.HSURBStartingAddress = pipeline->urb.vs_start,
|
|
.HSURBEntryAllocationSize = 0,
|
|
.HSNumberofURBEntries = 0);
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_URB_DS,
|
|
.DSURBStartingAddress = pipeline->urb.vs_start,
|
|
.DSURBEntryAllocationSize = 0,
|
|
.DSNumberofURBEntries = 0);
|
|
|
|
const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
|
|
/* The last geometry producing stage will set urb_offset and urb_length,
|
|
* which we use in 3DSTATE_SBE. Skip the VUE header and position slots. */
|
|
uint32_t urb_offset = 1;
|
|
uint32_t urb_length = (vue_prog_data->vue_map.num_slots + 1) / 2 - urb_offset;
|
|
|
|
#if 0
|
|
/* From gen7_vs_state.c */
|
|
|
|
/**
|
|
* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
|
|
* Geometry > Geometry Shader > State:
|
|
*
|
|
* "Note: Because of corruption in IVB:GT2, software needs to flush the
|
|
* whole fixed function pipeline when the GS enable changes value in
|
|
* the 3DSTATE_GS."
|
|
*
|
|
* The hardware architects have clarified that in this context "flush the
|
|
* whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
|
|
* Stall" bit set.
|
|
*/
|
|
if (!brw->is_haswell && !brw->is_baytrail)
|
|
gen7_emit_vs_workaround_flush(brw);
|
|
#endif
|
|
|
|
if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs))
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, .VSFunctionEnable = false);
|
|
else
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS,
|
|
.KernelStartPointer = pipeline->vs_vec4,
|
|
.ScratchSpaceBaseOffset = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX],
|
|
.PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
|
|
|
|
.DispatchGRFStartRegisterforURBData =
|
|
vue_prog_data->base.dispatch_grf_start_reg,
|
|
.VertexURBEntryReadLength = vue_prog_data->urb_read_length,
|
|
.VertexURBEntryReadOffset = 0,
|
|
|
|
.MaximumNumberofThreads = device->info.max_vs_threads - 1,
|
|
.StatisticsEnable = true,
|
|
.VSFunctionEnable = true);
|
|
|
|
const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
|
|
|
|
if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) {
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, .GSEnable = false);
|
|
} else {
|
|
urb_offset = 1;
|
|
urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset;
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS,
|
|
.KernelStartPointer = pipeline->gs_vec4,
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY],
|
|
.PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base),
|
|
|
|
.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1,
|
|
.OutputTopology = gs_prog_data->output_topology,
|
|
.VertexURBEntryReadLength = gs_prog_data->base.urb_read_length,
|
|
.DispatchGRFStartRegisterforURBData =
|
|
gs_prog_data->base.base.dispatch_grf_start_reg,
|
|
|
|
.MaximumNumberofThreads = device->info.max_gs_threads - 1,
|
|
/* This in the next dword on HSW. */
|
|
.ControlDataFormat = gs_prog_data->control_data_format,
|
|
.ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords,
|
|
.InstanceControl = gs_prog_data->invocations - 1,
|
|
.DispatchMode = gs_prog_data->base.dispatch_mode,
|
|
.GSStatisticsEnable = true,
|
|
.IncludePrimitiveID = gs_prog_data->include_primitive_id,
|
|
.ReorderEnable = true,
|
|
.GSEnable = true);
|
|
}
|
|
|
|
const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
|
|
if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
|
|
wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
|
|
anv_finishme("two-sided color needs sbe swizzling setup");
|
|
if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] != -1)
|
|
anv_finishme("primitive_id needs sbe swizzling setup");
|
|
|
|
/* FIXME: generated header doesn't emit attr swizzle fields */
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_SBE,
|
|
.NumberofSFOutputAttributes = pipeline->wm_prog_data.num_varying_inputs,
|
|
.VertexURBEntryReadLength = urb_length,
|
|
.VertexURBEntryReadOffset = urb_offset,
|
|
.PointSpriteTextureCoordinateOrigin = UPPERLEFT);
|
|
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PS,
|
|
.KernelStartPointer0 = pipeline->ps_ksp0,
|
|
.ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT],
|
|
.PerThreadScratchSpace = scratch_space(&wm_prog_data->base),
|
|
|
|
.MaximumNumberofThreads = device->info.max_wm_threads - 1,
|
|
.PushConstantEnable = wm_prog_data->base.nr_params > 0,
|
|
.AttributeEnable = wm_prog_data->num_varying_inputs > 0,
|
|
.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask,
|
|
|
|
.RenderTargetFastClearEnable = false,
|
|
.DualSourceBlendEnable = false,
|
|
.RenderTargetResolveEnable = false,
|
|
|
|
.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ?
|
|
POSOFFSET_SAMPLE : POSOFFSET_NONE,
|
|
|
|
._32PixelDispatchEnable = false,
|
|
._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL,
|
|
._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL,
|
|
|
|
.DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0,
|
|
.DispatchGRFStartRegisterforConstantSetupData1 = 0,
|
|
.DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2,
|
|
|
|
#if 0
|
|
/* Haswell requires the sample mask to be set in this packet as well as
|
|
* in 3DSTATE_SAMPLE_MASK; the values should match. */
|
|
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
|
|
#endif
|
|
|
|
.KernelStartPointer1 = 0,
|
|
.KernelStartPointer2 = pipeline->ps_ksp2);
|
|
|
|
/* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */
|
|
anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM,
|
|
.StatisticsEnable = true,
|
|
.ThreadDispatchEnable = true,
|
|
.LineEndCapAntialiasingRegionWidth = _05pixels,
|
|
.LineAntialiasingRegionWidth = _10pixels,
|
|
.EarlyDepthStencilControl = NORMAL,
|
|
.PointRasterizationRule = RASTRULE_UPPER_RIGHT,
|
|
.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode,
|
|
.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes);
|
|
|
|
*pPipeline = anv_pipeline_to_handle(pipeline);
|
|
|
|
return VK_SUCCESS;
|
|
}
|
|
|
|
VkResult gen7_compute_pipeline_create(
|
|
VkDevice _device,
|
|
const VkComputePipelineCreateInfo* pCreateInfo,
|
|
VkPipeline* pPipeline)
|
|
{
|
|
anv_finishme("primitive_id needs sbe swizzling setup");
|
|
abort();
|
|
}
|