Christian Gmeiner 081efcd68d etnaviv: isa: Split texkill into concrete bitset variants ... Replace the #instruction-alu-no-dst-maybe-src0-src1 intermediate, which used override expressions and variable SRC USE fields, with two concrete intermediates following the branch/branch_unary/branch_binary pattern: - #instruction-alu-no-dst-no-src: no sources, COND bits forced to zero - #instruction-alu-no-dst-cond-src0-src1: SRC0+SRC1 with fixed USE=1 patterns and a COND field The texkill instruction is split into texkill (unconditional, no sources) and texkill_cond (conditional, with sources). This eliminates the "maybe" anti-pattern and enables full assembler round-trip for conditional texkill. Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40205>		2026-03-05 12:42:22 +00:00
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disasm.cpp	etnaviv: isa: Split texkill into concrete bitset variants	2026-03-05 12:42:22 +00:00
meson.build	etnaviv: build dependency for the etnaviv tests	2024-08-26 08:09:15 +00:00