Samuel Pitoiset 07eba9a15a radv: do not lower loading TESS/ESGS rings using the ABI for LLVM ... LLVM uses an implicit argument for the ring offsets and this lowering was just broken. This fixes tessellation and geometry on all generations with LLVM. Fixes: 896a55f47d ("radv: Lower ABI in NIR for tess/ESGS/NGG shader arguments.") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16530>		2022-05-17 16:45:02 +00:00
..
addrlib	amd: add chip identification for gfx1100-1103	2022-05-10 04:29:55 +00:00
ci	radv/ci: re-enable fossils testing	2022-05-16 09:29:28 +00:00
common	radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export	2022-05-17 10:27:04 +00:00
compiler	aco/radv: drop radv_nir_compiler_options from aco.	2022-05-17 06:15:25 +00:00
drm-shim	Use proper types for meson objects	2022-04-18 13:03:08 +03:00
llvm	radv: do not lower loading TESS/ESGS rings using the ABI for LLVM	2022-05-17 16:45:02 +00:00
registers	amd: change chip_class naming to "enum amd_gfx_level gfx_level"	2022-05-13 14:56:22 -04:00
vulkan	radv: do not lower loading TESS/ESGS rings using the ABI for LLVM	2022-05-17 16:45:02 +00:00
.clang-format	radv: allow holes in inline push constants	2022-04-12 11:44:30 +00:00
meson.build	r300/r600: Add drm-shim support.	2022-02-02 00:59:08 +00:00