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b1862a0964
This commit just adds a miptail start field to isl_surf and wires it up in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code. We also add a minimum miptail LOD so that client drivers have a knob to control the miptails a bit. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
120 lines
4.7 KiB
C
120 lines
4.7 KiB
C
/*
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* Copyright 2020 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <stdint.h>
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#define __gen_address_type uint64_t
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#define __gen_user_data void
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static uint64_t
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__gen_combine_address(__attribute__((unused)) void *data,
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__attribute__((unused)) void *loc, uint64_t addr,
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uint32_t delta)
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{
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return addr + delta;
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}
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#include "isl_priv.h"
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#if GFX_VERx10 >= 125
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static const uint8_t isl_encode_tiling[] = {
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[ISL_TILING_4] = TILE4,
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[ISL_TILING_64] = TILE64,
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};
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#endif
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void
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isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch,
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const struct isl_cpb_emit_info *restrict info)
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{
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#if GFX_VERx10 >= 125
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if (info->surf) {
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assert((info->surf->usage & ISL_SURF_USAGE_CPB_BIT));
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assert(info->surf->dim != ISL_SURF_DIM_3D);
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assert(info->surf->tiling == ISL_TILING_4 ||
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info->surf->tiling == ISL_TILING_64);
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assert(info->surf->format == ISL_FORMAT_R8_UINT);
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}
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struct GENX(3DSTATE_CPSIZE_CONTROL_BUFFER) cpb = {
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GENX(3DSTATE_CPSIZE_CONTROL_BUFFER_header),
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};
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if (info->surf) {
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/* BSpec 46962 has a number of restriction on the fields of this packet
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* like :
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*
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* "The Width specified by this field must be less than or equal to
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* the surface pitch (specified in bytes via the Surface Pitch field).
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* For cube maps, Width must be set equal to Height.
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*
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* 1. The Width ofthis buffer must be the same as the Width of the
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* render target(s) (defined in SURFACE_STATE), unless Surface
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* Type is SURFTYPE_1D or SURFTYPE_2D with Depth = 0 (non-array)
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* and LOD = 0 (non-mip mapped).
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*
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* 2. Depth buffer (defined in 3DSTATE_DEPTH_BUFFER) unless either
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* the depth buffer or this buffer surf_typeare SURFTYPE_NULL"
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*
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* Unfortunately APIs like Vulkan do not give guarantees that every
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* framebuffer attachment will match in size (RT & CPB surfaces for
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* example). But at least it gives a guarantee that all the attachments
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* of a render pass will be at least be large enough to handle the
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* rendered area. So here we use the CPB surface values, even if they
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* don't strictly match the various BSpec restrictions.
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*/
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cpb.Width = (info->surf->logical_level0_px.width * 8) - 1;
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cpb.Height = (info->surf->logical_level0_px.height * 8) - 1;
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cpb.Depth = info->view->array_len - 1;
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cpb.RenderTargetViewExtent = cpb.Depth;
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cpb.SurfLOD = info->view->base_level;
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cpb.MinimumArrayElement = info->view->base_array_layer;
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cpb.SurfaceType = SURFTYPE_2D;
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cpb.SurfacePitch = info->surf->row_pitch_B - 1;
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cpb.MOCS = info->mocs;
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cpb.SurfaceQPitch = isl_surf_get_array_pitch_sa_rows(info->surf) >> 2;
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cpb.TiledMode = isl_encode_tiling[info->surf->tiling];
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cpb.SurfaceBaseAddress = info->address;
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cpb.MipTailStartLOD = info->surf->miptail_start_level;
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/* TODO:
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*
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* cpb.CPCBCompressionEnable is this CCS compression? Currently disabled
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* in isl_surf_supports_ccs() for CPB buffers.
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*/
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} else {
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cpb.SurfaceType = SURFTYPE_NULL;
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cpb.TiledMode = TILE64;
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}
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/* Pack everything into the batch */
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uint32_t *dw = batch;
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GENX(3DSTATE_CPSIZE_CONTROL_BUFFER_pack)(NULL, dw, &cpb);
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#else
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unreachable("Coarse pixel shading not supported");
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#endif
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}
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