Samuel Pitoiset 041cf2d48e radv: dirty the dynamic vertex input state only when needed ... This shouldn't be necessary when the VS doesn't have a prolog. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22944>		2023-05-12 06:20:02 +00:00
..
addrlib	amd: update addrlib	2023-03-29 20:36:09 +00:00
ci	radv/ci: stop setting MESA_SPIRV_LOG_LEVEL	2023-05-10 10:32:47 +00:00
common	radeonsi: Use vcn version instead of CHIP family for VCNs	2023-05-11 18:01:10 +00:00
compiler	aco: also reassign p_extract_vector post ra	2023-05-11 10:26:24 +00:00
drm-shim	amd/drm-shim: add amdgpu drm-shim	2023-05-11 00:58:02 +00:00
llvm	amd: Cleanup old GS intrinsics code.	2023-05-04 19:08:59 +00:00
registers	amd/registers: use gfx9 packet definitions for gfx940	2023-04-06 15:00:54 +00:00
vulkan	radv: dirty the dynamic vertex input state only when needed	2023-05-12 06:20:02 +00:00
.clang-format	amd: Add radv_foreach_stage to ForEachMacros.	2023-03-27 08:29:35 +00:00
meson.build	meson: build radeon drm-shim also for r300 and r600	2022-11-16 14:37:47 +00:00