Samuel Pitoiset 32c1e45718 radv: fix emitting VS prologs for merged shaders compiled separately on GFX10+ ... RSRC1 isn't equal to the VS RSRC1 and both config registers need to be re-emitted. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27574>		2024-02-13 14:01:42 +00:00
..
addrlib	amd/common: update addrlib for gfx11.5	2023-10-20 07:32:34 +00:00
ci	radv/ci: enable RADV_PERFTEST=shader_object on VEGA10	2024-02-13 09:14:21 +00:00
common	amd/common: Use the correct register table for GFX10_3	2024-02-12 14:04:24 +00:00
compiler	aco/gfx11+: limit hard clauses to 32 instructions	2024-02-13 13:40:52 +00:00
drm-shim	amd: Use align64 instead of ALIGN for 64 bit value parameter	2024-01-03 22:02:17 +00:00
llvm	ac/llvm: implement as_uniform and ballot_relaxed	2024-01-19 20:13:34 +00:00
registers	ac/registers: allow to parse GCVM_L2_PROTECTION_FAULT_STATUS	2023-10-30 08:10:22 +00:00
vpelib	amd/vpelib: Add UID for 3d Lut and control logic	2024-02-06 14:55:02 +00:00
vulkan	radv: fix emitting VS prologs for merged shaders compiled separately on GFX10+	2024-02-13 14:01:42 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00