mesa/src/intel
Caio Oliveira f18dee3618 intel/brw: Fallback to SEND from SEND_GATHER if possible
After optimization happen, if the sources are still in one or two
contigous spans for some reason (e.g. some data read from memory
now being written), it is beneficial to just use regular SEND
and avoid having to set the ARF scalar instruction.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32410>
2025-01-30 04:43:58 +00:00
..
blorp intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
ci anv/ci: Decrease anv-jsl-angle parallelism 2025-01-29 20:34:15 +00:00
common intel/common/xe2+: Allow SIMD32 PS for all multisample cases. 2025-01-29 23:39:32 +00:00
compiler intel/brw: Fallback to SEND from SEND_GATHER if possible 2025-01-30 04:43:58 +00:00
decoder intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
dev intel/brw: Use SHADER_OPCODE_SEND_GATHER in Xe3 2025-01-30 04:43:58 +00:00
ds intel : Expose Shader hashes for utrace and Perfetto 2025-01-10 17:38:16 +00:00
executor intel/executor: Fix typo when copying result into Lua table 2025-01-29 09:57:23 +00:00
genxml anv/xe3+: Set RegistersPerThread for bindless shader dispatch. 2025-01-29 23:39:32 +00:00
isl isl: use workaround framework for Wa_1207137018 2025-01-29 12:10:13 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf intel/perf: add new perf consts to support more metrics 2025-01-16 00:01:56 +00:00
shaders clc,libagx: automatically set lang version 2025-01-28 23:01:32 +00:00
tools intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
vulkan anv/xe3+: Enable VRT. 2025-01-29 23:39:32 +00:00
vulkan_hasvk hasvk: disable logic op for float/srgb formats 2025-01-29 08:02:21 +00:00
meson.build intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00