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Like other gen8+ hardware, the hardware automatically scales up thread counts.
We must be careful about the URB sizes since GT4 adds another slice.
One of the existing PCI IDs is actually mislabeled as GT3. Arguably this is a
real bug since the URB size will be wrong. Because this patch is simply meant to
add the missing IDs, that will be fixed in a later patch.
v2: No longer relevant.
v3: Update the wm thread count to support GT4. The WM thread count is used to
determine the maximum scratch space required. Currently the code always
allocates the maximum amount even though lower GT SKUs require less. The formula
is threads_per_psd * subslices_per_slice * slices
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
(cherry picked from commit
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| .. | ||
| i810_pci_ids.h | ||
| i915_pci_ids.h | ||
| i965_pci_ids.h | ||
| r200_pci_ids.h | ||
| r300_pci_ids.h | ||
| r600_pci_ids.h | ||
| radeon_pci_ids.h | ||
| radeonsi_pci_ids.h | ||
| vmwgfx_pci_ids.h | ||