Maximum number of simultaneous waves per core. Total number of IR3 instructions in the final generated shader executable. Total number of dwords in the final generated shader executable. Number of NOP instructions in the final generated shader executable. Number of MOV instructions in the final generated shader executable. Number of COV instructions in the final generated shader executable. Number of registers used in the final generated shader executable. Number of half-registers used in the final generated shader executable. The instruction where varying storage in Local Memory is released The instruction where helper invocations are killed SS bit is set for instructions which depend on a result of long instructions to prevent RAW hazard. SY bit is set for instructions which depend on a result of loads from global memory to prevent RAW hazard. A better metric to estimate the impact of SS syncs. A better metric to estimate the impact of SY syncs. Number of cat# instructions. Number of hardware loops Number of STore Private instructions in the final generated shader executable. Number of LoaD Private instructions in the final generated shader executable. Total number of IR3 instructions in the preamble. Whether the preamble will be executed early. Size of the const file in vec4 Instruction count Estimated ALU cycle count Estimated F16/F32/SCIB cycle count Estimated IC cycle count Binary size in bytes Number of 16-bit GPRs Number of 16-bit uniform registers Scratch size per thread in bytes Maximum number of threads in flight on a compute unit Number of hardware loops Number of spill (stack store) instructions Number of fill (stack load) instructions Preamble instruction count Instruction count Instruction bundles Register usage in vec4s Maximum number of threads in flight on a compute unit Binary size in quadwords Number of hardware loops Number of spill instructions Number of fill instructions Instruction count Tuple count Clause count Estimated normalized cycles Estimated normalized arithmetic cycles Estimated normalized Texture cycles Estimated normalized Load/Store cycles Estimated normalized Varying cycles Preload count Maximum number of threads in flight on a compute unit Binary size in bytes Number of hardware loops Number of spill instructions Number of fill instructions Cost of spill and fill instructions Number of registers used Uniform registers used Instruction count Estimated normalized cycles Estimated normalized FMA (Fused Multiply-Add) cycles Estimated normalized CVT (ConVerT) cycles Estimated normalized SFU (Special Function Unit) cycles Estimated normalized Varying cycles Estimated normalized Texture cycles Estimated normalized Load/Store cycles Binary size in bytes Maximum number of threads in flight on a compute unit Number of hardware loops Number of spill instructions Number of fill instructions Cost of spill and fill instructions Number of registers used Uniform registers used Number of QPU instructions Number of QPU threads dispatched Size of the spill buffer in bytes Number of times a register was spilled to memory Number of times a register was filled from memory Number of cycles the QPU stalls for a register read dependency Driver pipeline hash used by RGP Number of SGPR registers allocated per subgroup Number of VGPR registers allocated per subgroup Number of SGPR registers spilled per subgroup Number of VGPR registers spilled per subgroup Code size in bytes LDS size in bytes per workgroup Private memory in bytes per subgroup The maximum number of subgroups in flight on a SIMD unit Number of input slots reserved for the shader (including merged stages) Number of output slots reserved for the shader (including merged stages) CRC32 hash of code and constant data Instruction count Copy instructions created for pseudo-instructions Branch instructions Issue cycles plus stall cycles Estimated busy cycles to execute one wave Number of VMEM clauses (includes 1-sized clauses) Number of SMEM clauses (includes 1-sized clauses) SGPR usage before scheduling VGPR usage before scheduling Number of VALU instructions Number of SALU instructions Number of VMEM instructions Number of SMEM instructions Number of VOPD instructions Number of GEN instructions in the final generated shader executable. Code size in bytes Number of instructions in the final generated shader executable which access external units such as the constant cache or the sampler. Number of loops (not unrolled) in the final generated shader executable. Estimate of the number of EU cycles required to execute the final generated executable. This is an estimate only and may vary greatly from actual run-time performance. Number of scratch spill operations. This gives a rough estimate of the cost incurred due to spilling temporary values to memory. If this is non-zero, you may want to adjust your shader to reduce register pressure. Number of scratch fill operations. This gives a rough estimate of the cost incurred due to spilling temporary values to memory. If this is non-zero, you may want to adjust your shader to reduce register pressure. Number of bytes of scratch memory required by the generated shader executable. If this is non-zero, you may want to adjust your shader to reduce register pressure. Number of GRF registers required by the shader. Largest SIMD dispatch width. Maximum number of registers used across the entire shader. Number of bytes of workgroup shared memory used by this shader including any padding. Non SSA regs after NIR translation to BRW. Hash generated from shader source. Scheduling mode selected for this binary. Binary size in bytes Scratch size per instance in bytes Number of spilled registers per instance Number of allocated temp registers Number of not unrolled loops in the shader Total number of instruction groups Number of main instruction groups Number of bitwise instruction groups Number of control instruction groups