Maximum number of simultaneous waves per core. Total number of IR3 instructions in the final generated shader executable. Total number of dwords in the final generated shader executable. Number of NOP instructions in the final generated shader executable. Number of MOV instructions in the final generated shader executable. Number of COV instructions in the final generated shader executable. Number of registers used in the final generated shader executable. Number of half-registers used in the final generated shader executable. The instruction where varying storage in Local Memory is released The instruction where helper invocations are killed SS bit is set for instructions which depend on a result of long instructions to prevent RAW hazard. SY bit is set for instructions which depend on a result of loads from global memory to prevent RAW hazard. A better metric to estimate the impact of SS syncs. A better metric to estimate the impact of SY syncs. Number of cat# instructions. Number of STore Private instructions in the final generated shader executable. Number of LoaD Private instructions in the final generated shader executable. Total number of IR3 instructions in the preamble. Whether the preamble will be executed early. Instruction count Estimated ALU cycle count Estimated F16/F32/SCIB cycle count Estimated IC cycle count Binary size in bytes Number of 16-bit GPRs Number of 16-bit uniform registers Scratch size per thread in bytes Maximum number of threads in flight on a compute unit Number of hardware loops Number of spill (stack store) instructions Number of fill (stack load) instructions Instruction count Instruction bundles Register usage in vec4s Maximum number of threads in flight on a compute unit Binary size in quadwords Number of hardware loops Number of spill instructions Number of fill instructions Instruction count Tuple count Clause count Estimated normalized cycles Estimated normalized arithmetic cycles Estimated normalized Texture cycles Estimated normalized Load/Store cycles Estimated normalized Varying cycles Preload count Maximum number of threads in flight on a compute unit Binary size in bytes Number of hardware loops Number of spill instructions Number of fill instructions Instruction count Estimated normalized cycles Estimated normalized FMA (Fused Multiply-Add) cycles Estimated normalized CVT (ConVerT) cycles Estimated normalized SFU (Special Function Unit) cycles Estimated normalized Varying cycles Estimated normalized Texture cycles Estimated normalized Load/Store cycles Binary size in bytes Maximum number of threads in flight on a compute unit Number of hardware loops Number of spill instructions Number of fill instructions Number of QPU instructions Number of QPU threads dispatched Size of the spill buffer in bytes Number of times a register was spilled to memory Number of times a register was filled from memory Number of cycles the QPU stalls for a register read dependency