Commit graph

134436 commits

Author SHA1 Message Date
Eric Anholt
f1403d66d4 swrast: Use util_format_write_4/4ub for the scattered pixel writes.
This was the only code using the "get a pack-a-pixel function pointer"
generated code, switch it over to using util/format's.

This does mean some more format desc lookups in the loop, but this code is
only accessible from classic driver swrast fallbacks at this point, where
GPU read perf completely dominates the profile anyway.

basically no change to driver size.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8532>
2021-01-19 20:02:51 +00:00
Samuel Pitoiset
4c99d6ff54 radv: flush L2 for images affected by the pipe misaligned issue on GFX10+
In some rare cases, L2 needs to be flushed if an image is affected
by the pipe misaligned issue. This is roughly based on AMDVLK.

I confirmed that disabling TC-compat HTILE, and respectively DCC,
for the relevant images also fixes the regressions below.

This fixes some regressions introduced with L2 coherency for
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_* and for
dEQP-VK.renderpass2.suballocation.multisample_resolve.*.

Fixes: 4a783a3c78 ("radv: Use L2 coherency on GFX9+.")
Co-Authored-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8557>
2021-01-19 19:51:44 +00:00
Samuel Pitoiset
8882abe47e radv: restore invalidating the vector cache for internal meta operations
The driver used to invalidate the vector cache for meta operations
but this has been removed and I think it should be restored to fix
a bunch of regressions on GFX8.

This probably needs to be cleaned up but this is a hotfix.

This fixes a bunch of regressions and flakes on GFX8 like
dEQP-VK.pipeline.multisample.sample_locations_ext.draw.color.samples_4.*.

Fixes: 8f8d72af55 ("radv: Use access helpers for flushing with meta operations.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8573>
2021-01-19 19:15:39 +00:00
Samuel Pitoiset
c28401ab43 radv: enable TC-compat HTILE for D16S8 on GFX9+
I don't know why this wasn't enabled but I think it should be.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8562>
2021-01-19 18:16:35 +00:00
Samuel Pitoiset
cc5b6a0e89 radv: enable TC-compat HTILE with D32S8 and MSAA on GFX9+
Only GFX8 has some depth/stencil resolve failures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8562>
2021-01-19 18:16:35 +00:00
Samuel Pitoiset
60ead6e04b radv: add a comment explaining the micro tile mode resolve
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8558>
2021-01-19 18:52:43 +01:00
cheyang
3e13c1f8df frontend/dri: fix doesn't support RGBA ordering still expose RGBA in config
Signed-off-by: cheyang <cheyang@bytedance.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8553>
2021-01-19 17:10:47 +00:00
Rhys Perry
4c1953a9b8 aco: add test for incorrect convert_to_SDWA() check
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8577>
2021-01-19 15:38:56 +00:00
Rhys Perry
fcda9b6737 aco: fix convert_to_SDWA() check in add_subdword_definition()
v_or_b32 with a v2b definition should use SDWA if is_partial=true.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 56345b8c61 ("aco: allow reading/writing upper halves/bytes when possible")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8577>
2021-01-19 15:38:51 +00:00
Mike Blumenkrantz
5ebfb9cd60 zink: process ubos with location values set as long as they're actually ubos
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8514>
2021-01-19 14:14:59 +00:00
Mike Blumenkrantz
9eec52c67e zink: tweak xfb slot mapping in ntv
ARB_enhanced_layouts allows specifying overlapping variable locations
for xfb outputs, so we need to explode the arrays here to a full 128
components so we can do per-component mapping

sometimes this fails though, as in the case where xfb is just selecting
a single component from a vec but still considering the whole slot, and
so for those cases we just decrement our array index until we get to the
base, which will be within 3 components

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8515>
2021-01-19 14:06:31 +00:00
Abhishek Kumar
276e3927b5 intel: change urb max shader geometry for CML GT1
Below deqp cts failure is seen on CML GT1 only , GT2 all test
passes, changing the max shader geometry to 256 (previous 640)
fixes all failure tests.Similar issue on BDW GT1
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3173

dEQP-GLES31.functional.geometry_shading.layered.
		render_with_default_layer_cubemap
		render_with_default_layer_3d
		render_with_default_layer_2d_array

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4102

Signed-off-by: Abhishek Kumar <abhishek4.kumar@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8550>
2021-01-19 13:37:35 +00:00
Iago Toral Quiroga
14651edbab v3dv: use PIPE_TIMEOUT_INFINITE
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8554>
2021-01-19 11:54:22 +01:00
Iago Toral Quiroga
e122c9f3c8 v3dv: don't wait for idle on occlusion query pool resets
Instead, wait for the specific queries being reset to
not be in use by the GPU.

This takes query pool resets in the UE4 Shooter demo from
50-60ms down to 0.5-2ms.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8554>
2021-01-19 11:54:22 +01:00
Iago Toral Quiroga
15cf2ab642 v3dv: disable early Z writes if Z writes are disabled
I saw this while inspecting CL dumps from the UE Shooter demo,
where they disable Z writes for occlusion queries. The hardware
is probably doing this internally, but it doesn't hurt
to do this explicitly and make CL traces consistent with intended
behavior.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8571>
2021-01-19 10:08:27 +00:00
Pierre-Eric Pelloux-Prayer
41d22eb68e radeonsi: inhibit clockgating when using SQTT
Ported from PAL.

Fixes: 07c1504d1b ("radeonsi: implement SQTT support")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8480>
2021-01-19 09:52:08 +01:00
Iago Toral Quiroga
a46547671b v3dv: only update uniforms for dirty descriptors if stage has descriptors
If we have dirty descriptor set state we have to update our uniform
data to reference the new resources such as addresses for textures
or UBOs. This is known to have a high CPU cost, so we want to limit
this as much as we can.

It is a common rendering pattern in applications to render many objects
using the same pipeline, but modifying the descriptor sets bound to update
textures, UBOs, etc. In this scenario, we would be incurring in unnecessary
uniform stream updates for stages that don't access descriptor sets at all.

This change makes it so we track which shader stages in a pipeline
use descriptor set state and skips updating uniform streams for them
when dirty descriptor set state is the only reason requiring us to
generate new uniform streams for a draw call.

v2: reuse shader stage information from the pipeline set layouts
    to track shader stages that use descriptor state.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8555>
2021-01-19 08:07:57 +00:00
Samuel Pitoiset
c3ac6f7cd7 radv: flush L2 metadata as part of CB/DB flush instead of CS_DONE on GFX9
This restores the previous logic because L2 coherency was fully
implemented. It appears that flushing L2 metadata with a CS_DONE
event hangs.

This fixes GPU hangs with Monster Hunter World.

Fixes: 4a783a3c ("radv: Use L2 coherency on GFX9+.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8566>
2021-01-19 07:47:34 +01:00
Vinson Lee
3e6b37a954 nv50/ir: Initialize DataArray members in constructor.
Fix defects reported by Coverity Scan.

uninit_member: Non-static class member array is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member arrayIdx is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member baseAddr is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member arrayLen is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member baseSym is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member vecDim is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member eltSize is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member file is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member regOnly is not initialized in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7764>
2021-01-18 18:12:22 -08:00
Bas Nieuwenhuizen
c4ea4e026b radv: Add a trivial implementation of VK_KHR_deferred_host_operation
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8545>
2021-01-19 01:25:38 +01:00
Marek Olšák
290dcb26ae mesa: fix alpha channel of ETC2_SRGB8 decompression for !bgra
If software decompression is used for ETC2, the alpha channel
for sRGB8 textures would be set only if BGRA is true.

Fixes: e5604ef78b "st/mesa/i965: Allow decompressing ETC2 to GL_RGBA"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8529>
2021-01-18 17:18:20 -05:00
Icecream95
5eb39dd95f pan/bi: Iterate from zero when setting RA interference
It is now valid for a node to have an index of zero.

Fixes: 39aa8c4a5a ("pan/bi: Switch to new IR")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig
a63960b7f3 pan/bi: Fix printing of node 0
Fixes: 1893a3805e ("pan/bi: Generate instruction printer")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig
3a16ab84e2 pan/bi: Fix RA of node 0
Fixes: 39aa8c4a5a ("pan/bi: Switch to new IR")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig
92461a1133 pan/bi: Fix 64-bit SSBO addresses
Fixes: 9c7efc4510 ("pan/bi: Add intrinsic emits for builder")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
a8c91f15f0 pan/mdg: Fix spilling when scratch memory is used
Add the tls_size from NIR before spilling so that it doesn't alias
with spill slots.

Fixes: 152bc5d15e ("pan/mdg: Support loads and stores to scratch memory")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
6f0eff548c pan/bi: Implement packing ops between 32-bit vec1 and 16-bit vec2
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
c9c637a707 pan/bi: Implement ihadd/irhadd operations
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
591ccbcf47 pan/bi: Implement saturated add/sub operations
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
7258b4b48d panfrost: Set TLS for compute jobs
Fixes CL programs using scratch storage, such as the Piglit test
i32-stack-array.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
3f7e7495fc pan/bi: Lower umul_high
Also lower uadd_carry, which the mul_high lowering generates.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
2e372d0c3b pan/bi: Add w0 to the 'h01' swizzle bucket
A number of instructions, such as LOAD.i8, use this swizzle in the XML.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
2ec0897b11 pan/mdg: Allow 64-bit src_bitsize for comparison operations
Fixes Piglit test attributes.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
b5d6e5049f pan/mdg: Don't reorder loads/stores past each other
Fixes Piglit test local-memory.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
24fcc032ef pan/mdg: Limit int64 vectorization
Previously, nir_opt_vectorize was sometimes vectorizing 64-bit
load_const instructions to vec4.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
f0109e9ac0 panfrost: Assert on sysval overflow
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
24867386ee panfrost: Add a sysval for local_work_dim
Fixes Piglit test get-work-dim.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
f5a35918db panfrost: Add a sysval for local_group_size
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
76fa57d195 pan/bi: Use pan_nir_lower_64bit_intrin
The intrinsics covered by the pass are implemented by reading 32-bit
registers, so there is no reason to keep them 64-bit.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
7c2308769b panfrost: Use the correct NIR options for OpenCL on Bifrost
This is needed so that 64-bit operations are lowered properly.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
c82ab9b94a pan/bi: Improve unknown intrinsic error
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
56f753f8e2 panfrost: Set bifrost_props for compute shaders
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
c71d4d931e pan/bi: Implement load_kernel_input
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
f33694552d pan/bi: Implement load/store intrinsics
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
58cf95a637 pan/bi: Improve interoperability of the command-line disassembler
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
7c6aa5f49d pan/bi: Set compute lowering options
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
d267183829 pan/bi: Add some compute intrinsic loads
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
2a7c33bd9d pan/bi: Handle 64-bit pack and unpack operations
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Icecream95
f5c9a10f33 pan/bi: Lower 64-bit integers
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig
f4d2b35ac8 pan/bi: Pipe scratch_size in from NIR
Needs to be added to whatever we spill ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
2021-01-18 20:49:45 +00:00