Commit graph

15 commits

Author SHA1 Message Date
Eric Anholt
028f6b327c broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).
The V3D 3.x series of TMU writes with meaning depending on the texture
type is replaced with writes to specific registers for each texture
argument semantic.
2018-01-12 21:56:48 -08:00
Eric Anholt
f50d39ab49 broadcom/vc5: Add a test for .ifb in ADD ops.
I had a .ifb being decoded weird in sampid, so this is to check that .ifb
is fine.
2018-01-12 21:54:57 -08:00
Eric Anholt
267f13dbee broadcom/vc5: Add the new tesselation opcodes in V3D 4.1. 2018-01-12 21:54:50 -08:00
Eric Anholt
22a02f3e34 broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.
Now, instead of a magic write register for VPM stores we have an
instruction to do them (which means no packing of other ALU ops into it),
with the ability to reorder the VPM stores due to the offset being baked
into the instruction.

VPM loads also gain the ability to be reordered by packing the row into
the A argument.  They also no longer write to the r3 accumulator, and
instead must be stored to a physical register.
2018-01-12 21:54:33 -08:00
Eric Anholt
55f8a01aca broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.
I had all the packing code in this file at one point, but these defines
now live in qpu_pack.c.
2018-01-12 21:54:27 -08:00
Eric Anholt
2bd378647b broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates. 2018-01-12 21:54:18 -08:00
Eric Anholt
c81cc767e4 broadcom/vc5: Drop signal bit #defines.
Signals are more complicated than that, and tables ended up being better.
2018-01-12 21:53:53 -08:00
Eric Anholt
dfee62eed3 broadcom/vc5: Add support for V3Dv4 signal bits.
The WRTMUC replaces the implicit uniform loads in the first two texture
instructions.  LDVPM disappears in favor of an ALU op.  LDVARY, LDTMU,
LDTLB, and LDUNIF*RF now write to arbitrary registers, which required
passing the devinfo through to a few more functions.
2018-01-12 21:53:45 -08:00
Eric Anholt
81ec2ba229 broadcom/vc5: Fix pack/unpack of vfmul input unpack flags. 2018-01-12 21:53:38 -08:00
Dylan Baker
4ccb981673 meson: Use consistent style for tests
Don't use intermediate variables, use consistent whitespace.

Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
2018-01-11 15:40:02 -08:00
Eric Anholt
49e2586bfc broadcom/vc5: Fix a typo in memcmp for sig unpack checking.
This shockingly ended up working out, because only the first byte of *sig
is used and (sizeof(*sig) != 0) == 1.  Fixes a compiler warning.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=104183
2017-12-14 14:36:24 -08:00
Eric Anholt
dfff9ce45e broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.
The v3d_qpu_writes_r*() were only checking for fixed-function accumulator
writes, not normal ALU writes to those regs.

Fixes fs-discard-exit-2 on simulation (but not HW).
2017-11-07 12:57:49 -08:00
Eric Anholt
48615d1ead meson: Fix vc5 deps on the XML-generated headers.
I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the
v3d_packet_v33_pack.h that the compiler and QPU packing actually use.
2017-10-20 17:16:00 -07:00
Eric Anholt
4f3e380fa0 meson: Add support for the vc5 driver.
v2: Default vc5 to off, since it requires the simulator currently.  Add
    missing dep on the XML generation from libbroadcom_vc5.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com> (v1)
2017-10-17 13:41:59 -07:00
Eric Anholt
05c7d9715b broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.
Unlike VC4, I've defined an unpacked instruction format with pack/unpack
functions to convert to 64-bit encoded instructions.  This will let us
incrementally put together our instructions and validate them in a more
natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to.

The pack/unpack unfortuantely are written by hand.  While I could define
genxml for parts of it, there are many special cases (like operand order
of commutative binops choosing which binop is being performed!) and it
probably wouldn't come out much cleaner.

The disasm unit test ensures that we have the same assembly format as
Broadcom's internal tools, other than whitespace changes.

v2: Fix automake variable redefinition complaints, add test to .gitignore
2017-10-10 11:42:04 -07:00