Nanley Chery
f93bc14618
intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable
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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 10:47:05 -07:00
Nanley Chery
6312328a61
intel: Use RENDER_SURFACE_STATE::DepthStencilResource
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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 10:47:05 -07:00
Rafael Antognolli
43b48ee752
intel/blorp/gen12: Set FWCC when storing the clear color.
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From "Render Target Fast Clear" description for Gen12:
"SW must store clear color using MI_STORE_DATA_IMM with
ForceWriteCompletionCheck bit set."
From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1):
"Following the last write from this command, Command Streamer
will wait for all previous writes are completed and in global
observable domain before moving to next command."
We use 4 SDIs to store the clear color (one per channel). From the
description, it looks to me that setting that flag only on the last SDI
should be enough.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 10:47:05 -07:00
Plamena Manolova
1ecd37eac6
genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.
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In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction
which enables support for depth bounds testing.
Signed-off-by: Plamena Manolova <plamena.manolova@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 13:45:24 +00:00
Jordan Justen
109c96b322
genxml/gen12: Add AUX MAP register definitions
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 00:09:13 -07:00
Lionel Landwerlin
a2a1873a82
intel/genxml: add RPSTAT register for core frequency
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-10-23 05:41:15 +00:00
Jason Ekstrand
9dd9c3363b
intel/genxml: Remove W-tiling on gen12
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It's no longer supported by the hardware
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-10-17 14:47:22 -07:00
Jordan Justen
523ba0a3e7
intel/genxml,isl: Add gen12 stencil buffer changes
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Rework:
* NULL stencil buffer path (Jason)
* genxml fixes (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-10-17 14:47:22 -07:00
Jordan Justen
d2a490d1d9
intel/genxml,isl: Add gen12 depth buffer changes
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Reworks:
* Fix 3DSTATE_DEPTH_BUFFER "Surface Format" end in xml (Jason)
* Remove WM_HZ_OP changes (Nanley)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-10-17 14:47:22 -07:00
Jordan Justen
6c9f9a82d7
intel/genxml,isl: Add gen12 render surface state changes
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-10-17 14:47:17 -07:00
Anuj Phogat
ee2bde5232
genxml/gen11+: Add COMMON_SLICE_CHICKEN4 register
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Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-09-11 11:29:37 -07:00
Jordan Justen
9790cfcefa
anv,iris: L3ALLOC register replaces L3CNTLREG for gen12
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-09-06 13:11:25 -07:00
Jordan Justen
531563b64b
intel/genxml: Add gen12.xml as a copy of gen11.xml
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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-08-28 13:38:32 -07:00
