Commit graph

15202 commits

Author SHA1 Message Date
Matt Turner
3d661e6062 i965: Test instruction compaction on all supported Gens
Note that there's no point in testing on G45, since its compaction is
the same as Gen5. Same logic applies to Gen7 variants and low-power
parts.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
9ff7d9b853 i965: Silence signed/unsigned comparison warning
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
eac89911e5 i965: Move compaction "prepass" into brw_eu_compact.c
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
17641f6388 i965: Mark src inst pointer const in compaction code
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Topi Pohjolainen
393ec1a507 intel/blorp: Adjust intra-tile x when faking rgb with red-only
v2 (Jason): Adjust directly in surf_fake_rgb_with_red()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-08-21 09:55:08 +03:00
Kenneth Graunke
6f8a577ed2 anv: Use ISL for emitting null surface states.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:48 -07:00
Kenneth Graunke
5db9757bd7 isl: Add a null surface fill function.
ISL already offers functions to fill out most kinds of SURFACE_STATE,
so why not handle null surfaces too?

Null surfaces are simple, so we can just take the dimensions, rather
than an entirte fill structure.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:36 -07:00
Eric Anholt
9caba0f16f anv: Move a comment that got left behind in the u_vector refactor. 2017-08-18 11:56:58 -07:00
Jason Ekstrand
1af8342b0c intel/isl: Replace switch statements of doom with a macro
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-17 18:09:05 -07:00
Jason Ekstrand
2d68d27071 intel/isl: Reduce header file duplication
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-17 18:09:05 -07:00
Jason Ekstrand
bf1d2e84f3 anv/gem: Add a stub for sync_file_merge
This fixes make check

Fixes: 5c4e4932e0
2017-08-16 18:44:26 -07:00
Jason Ekstrand
98983503cb anv: Advertise VK_KHR_external_semaphore
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Jason Ekstrand
55bce22d8d anv: Use DRM sync objects for external semaphores when available
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Jason Ekstrand
f41a0e4b0d anv/gem: Add a drm syncobj support
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Jason Ekstrand
5c4e4932e0 anv: Implement support for exporting semaphores as FENCE_FD
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Jason Ekstrand
e4054ab77b anv/gem: Use EXECBUFFER2_WR when the FENCE_OUT flag is set
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Jason Ekstrand
017cdb10cf anv: Submit a dummy batch when only semaphores are provided.
Vulkan allows you to do a submit whose only job is to wait on and
trigger semaphores.  The easiest way for us to support that right
now is to insert a dummy execbuf.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Jason Ekstrand
031f57eba3 anv: Add a basic implementation of VK_KHX_external_semaphore
This patch adds an implementation based on DRM BOs.  We don't actually
advertise the extension yet because we want to add a couple more paths
first.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-15 19:08:26 -07:00
Scott D Phillips
d6539608a4 intel/genxml: Fix gen10 BLEND_STATE variable length packing
BLEND_STATE packing was modified to be variable-length in:

 9670124e31 genxml: Make BLEND_STATE command support variable length array.

The initial gen10.xml still had the old, fixed-length style
definition for BLEND_STATE. So gen10_upload_blend_state would
overwrite the packed BLEND_STATE_ENTRYs with its own fixed array
of all-zero entries when packing BLEND_STATE. This caused
BLEND_STATE upload to not work at all.

Fixes: aa416f515a ("i965/genxml: Add gen10.xml")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-08-15 09:06:29 -07:00
Ben Widawsky
8f6e54c929 i965: Pretend that CCS modified images are two planes
v2: move is_aux into if block. (Jason)
Use else block instead of goto (Jason)

v3: Fix up logic for is_aux (Ben)
Fix up size calculations and add FIXME (Ben)

v4 (Jason Ekstrand):
Use the aux_pitch in the image instead of calculating it

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-08-14 10:43:30 -07:00
Jason Ekstrand
cf2e92262b intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-08-14 10:43:30 -07:00
Iago Toral Quiroga
81615ad444 intel/compiler: properly size attribute wa_flags array for Vulkan
Mesa will map user defined vertex input attributes to slots
starting at VERT_ATTRIB_GENERIC0 which gives us room for only 16
slots (up to GL_VERT_ATTRIB_MAX). This sufficient for GL, where
we expose exactly 16 vertex attributes for user defined inputs, but
in Vulkan we can expose up to 28 (which are also mapped from
VERT_ATTRIB_GENERIC0 onwards) so we need to account for this when
we scope the size of the array of attribute workaround flags
that is used during the brw_vertex_workarounds NIR pass. This
prevents out-of-bounds accesses in that array for NIR shaders
that use more than 16 vertex input attributes.

Fixes:
dEQP-VK.pipeline.vertex_input.max_attributes.*

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-11 10:41:44 +02:00
Kenneth Graunke
5563872dbf isl: Validate row pitch of stencil surfaces.
Also, silence an obnoxious finishme that started occurring for all
GL applications which use stencil after the i965 ISL conversion.

v2: Check against 3DSTATE_STENCIL_BUFFER's pitch bits when using
    separate stencil, and 3DSTATE_DEPTH_BUFFER's bits when using
    combined depth-stencil.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-10 15:18:58 -07:00
Jason Ekstrand
4d27c6095e intel/isl: Don't align the height of the last array slice
We were calculating the total height of 2D surfaces by multiplying the
row pitch by the number of slices.  This means that we actually request
slightly more space than actually needed since the padding on the last
slice is unnecessary.  For tiled surfaces this is not likely to make a
difference.  For linear surfaces, on the other hand, this means we may
require additional memory.  In particular, this makes the i965 driver
reject EGL imports of buffers which do not have this extra padding.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-07 09:31:11 -07:00
Jason Ekstrand
c15b92ce11 intel/isl: Stop padding surfaces
The docs contain a bunch of commentary about the need to pad various
surfaces out to multiples of something or other.  However, all of those
requirements are about avoiding GTT errors due to missing pages when the
data port or sampler accesses slightly out-of-bounds.  However, because
the kernel already fills all the empty space in our GTT with the scratch
page, we never have to worry about faulting due to OOB reads.  There are
two caveats to this:

 1) There is some potential for issues with caches here if extra data
    ends up in a cache we don't expect due to OOB reads.  However,
    because we always trash the entire cache whenever we need to move
    anything between cache domains, this shouldn't be an issue.

 2) There is a potential issue if a surface gets placed at the very top
    of the GTT by the kernel.  In this case, the hardware could
    potentially end up trying to read past the top of the GTT.  If it
    nicely wraps around at the 48-bit (or 32-bit) boundary, then this
    shouldn't be an issue thanks to the scratch page.  If it doesn't,
    then we need to come up with something to handle it.

Up until some of the GL move to ISL, having the padding code in there
just caused us to harmlessly use a bit more memory in Vulkan.  However,
now that we're using ISL sizes to validate external dma-buf images,
these padding requirements are causing us to reject otherwise valid
images due to the size of the BO being too small.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-07 09:31:11 -07:00
Jason Ekstrand
06d3115bb9 anv/formats: Allow sampling on depth-only formats on gen7
We can't sample from depth-stencil formats but on gen7 but we can sample
from depth-only formats.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102024
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
2017-08-07 08:27:09 -07:00
Chris Wilson
6c530ad116 i965: Reduce passing 2x32b of reloc_domains to 2 bits
The kernel only cares about whether the object is to be written to or
not, only reduces (reloc.read_domains, reloc.write_domain) down to just
!!reloc.write_domain. When we use NO_RELOC, the kernel doesn't even read
those relocs and instead userspace has to pass that information in the
execobject.flags. We can simplify our reloc api by also removing the
unused read/write domains and only pass the resultant flags.

The caveat to the above are when we need to make the kernel aware that
certain objects need to take into account different work arounds.
Previously, this was done using the magic (INSTRUCTION, INSTRUCTION)
reloc domains. NO_RELOC requires this to be passed in the execobject
flags as well, and now we push that up the callstack.

The API is more compact, more expressive of what happens underneath, but
unfortunately requires more knowledge of the system at the point of use.
Conversely it also means that knowledge is specific and not generally
applied and so not overused.

   text	   data	    bss	    dec	    hex	filename
8502991	 356912	 424944	9284847	 8dacef	lib/i965_dri.so (before)
8500455	 356912	 424944	9282311	 8da307	lib/i965_dri.so (after)

v2: (by Ken) Rebase.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-04 10:26:37 -07:00
Juan A. Suarez Romero
86c68e0a33 anv: Makefile.vulkan.am: ICD json files are now generated with python
Commit 0ab04ba979 (anv: Use python to generate ICD json files) changed
the way ICD json files are created.

Remove the old .in files from extra dist, and add the python script.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-04 09:54:46 +02:00
Lionel Landwerlin
1006cd512d anv: put anv_extensions.c in gitignore
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-03 16:14:45 +01:00
Tapani Pälli
ca6237eb4f android: anv_extensions.c is generated to libmesa_vulkan_common
Fixes build error with anv_extensions.c not found for
libmesa_anv_entrypoints.

Fixes: d62063c "anv: Autogenerate extension query and lookup"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-03 13:09:59 +03:00
Dave Airlie
271fa3a684 intel/vec4/gs: reset nr_pull_param if DUAL_INSTANCED compile failed.
If dual object compile fails (as seems to happen with virgl a
fair bit, and does piglit even have any tests for it?), we end up
not restarting the pull params, so we call
vec4_visitor::move_uniform_array_access_to_pull_constant
a second time and it runs over the ends of the alloc.

Fixes: tests/spec/glsl-1.50/execution/geometry/max-input-components.shader_test
running inside virgl on ivybridge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-08-03 16:54:08 +10:00
Matt Turner
858f554078 i965: Fix indentation 2017-08-02 16:49:32 -07:00
Jason Ekstrand
277644221d anv: Advertise VK_KHR_relaxed_block_layout
There is literally no work for us to do here.  It already just works in
our driver.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-02 09:13:13 -07:00
Jason Ekstrand
600605e3fc anv: Bump the advertised version to 1.0.57
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-02 09:13:13 -07:00
Jason Ekstrand
077b200096 anv: Pull the API version from anv_extensions.py
This way everything stays in sync and we only have the one version
number.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-02 09:13:13 -07:00
Jason Ekstrand
0ab04ba979 anv: Use python to generate ICD json files
This is more lines of code but the python is far easier to read than the
sed expressions we were using before.  Also, this allows us to pull the
API version from anv_entrypoints.py so it never gets out-of-sync.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-02 09:13:13 -07:00
Jason Ekstrand
7382d8a416 anv: Add MAX_API_VERSION to anv_extensions.py
The VkVersion class is probably overkill but it makes it really easy to
compare versions in a way that's safe without the caller having to think
about patch vs. no patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-02 09:13:13 -07:00
Jason Ekstrand
a25267654b anv: Make some bits of anv_extensions module-private
This way we can use "from anv_extensions import *" in the entrypoint
generator without worrying too much about pollution

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-02 09:13:13 -07:00
Tapani Pälli
99c764b647 intel: move gen_decoder.* back to COMMON_FILES
this change reverts commit 4f695731, we want to be able to build
with -DDEBUG and gen_decoder on Android.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-02 10:31:13 +03:00
Tapani Pälli
9bd15da85d android: link libmesa_intel_common with zlib and expat
Makes it possible to build Mesa on Android with -DDEBUG with
the next patch that reverts 4f695731.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-02 10:30:50 +03:00
Jason Ekstrand
d62063ce31 anv: Autogenerate extension query and lookup
As time goes on, extension advertising is going to get more complex.
Today, we either implement an extension or we don't.  However, in the
future, whether or not we advertise an extension will depend on kernel
or hardware features.  This commit introduces a python codegen framework
that generates the anv_EnumerateFooExtensionProperties functions as well
as a pair of anv_foo_extension_supported functions for querying for the
support of a given extension string.  Each extension has an "enable"
predicate that is any valid C expression.  For device extensions, the
physical device is available as "device" so the expression could be
something such as "device->has_kernel_feature".  For instance
extensions, the only option is VK_USE_PLATFORM defines.

This mechanism also means that we have a single one-line-per-entry table
for all extension declarations instead of the two tables we had in
anv_device.c and the one we had in anv_entrypoints_gen.py.  The Python
code is smart and uses the XML to determine whether an extension is an
instance extension or device extension.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-01 11:12:41 -07:00
Jason Ekstrand
ddc86c1d0e anv: Add a new centralized extensions file
This will allow us to keep everything in one place when it comes to
declaring what extensions are supported.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-08-01 11:12:41 -07:00
Iago Toral Quiroga
31f1863ace anv: only expose up to 28 vertex attributes
The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs.
However, the maximum allowed value of "Vertex URB Entry Read Length"
in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements.
Because we also need to reserve a vertex buffer to upload
VertexIndex/InstanceIndex and another to upload DrawID when needed,
we can only expose 28.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-26 08:16:43 +02:00
Iago Toral Quiroga
a848e693ef anv/cmd_buffer: fix off by one error in assertion
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-26 08:02:06 +02:00
Eric Anholt
decd2b32aa intel/decoder: Reuse the gen_make_gen() helper.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-25 14:44:52 -07:00
Eric Anholt
19ffa4bfb2 intel/decoder: Reuse the MAX2 macro instead of defining another one.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-25 14:44:52 -07:00
Emil Velikov
5d47dd9c2a intel/blorp: ship blorp_genX_exec.h within the tarball
Fixes: c9cb37b2a6 ("intel/blorp: Add a partial resolve pass for MCS")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-24 15:14:21 +01:00
Jason Ekstrand
6874b953f6 anv/image: zalloc image views
This allows us to avoid some extra zeroing.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22 21:41:12 -07:00
Jason Ekstrand
a1cad8218e anv/image: Use vk_zalloc instead of an explicit memset
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22 21:41:12 -07:00
Jason Ekstrand
1e32c8303a anv: Separate surface states by layout instead of aux_usage
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22 21:41:12 -07:00