Commit graph

39177 commits

Author SHA1 Message Date
Iago Toral Quiroga
1a99fc0fd0 v3d: fix glDrawTransformFeedback{Instanced}()
This needs to take the vertex count from the provided transform
feedback buffer.

v2:
 - don't take the vertex count from the underlying buffer, instead,
   take it from a v3d subclass of pipe_stream_output_target (Eric).

Fixes piglit tests:
spec/ext_transform_feedback2/draw-auto
spec/ext_transform_feedback2/draw-auto instanced

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-26 08:29:41 +02:00
Iago Toral Quiroga
47eb74ae00 v3d: subclass pipe_streamout_output_target to record TF vertices written
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-26 08:29:41 +02:00
Iago Toral Quiroga
39df568ca1 v3d: refactor v3d_tf_statistics_record slightly
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-26 08:29:41 +02:00
Alyssa Rosenzweig
2f9236096a Revert "panfrost: Don't DIY point size/coord fields"
This reverts commit 4508f43eed, which
broke a bunch of dEQP tests (e.g. in
dEQP-GLES2.functional.draw.draw_arrays.*)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 13:17:22 -07:00
Kenneth Graunke
0e24d10ff5 iris: Use gen_mi_builder to handle CS ALU operations.
In a few cases, we switch to MI_MATH instead of MI_PREDICATE,
just because we were already doing math and it's easier to chain
together.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-25 18:42:55 +00:00
Kenneth Graunke
fe7ed6b057 iris: Make iris_query.c a genxml-compiled file.
This will let us use Jason's new MI-builder shortly.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-25 18:42:55 +00:00
Kenneth Graunke
975f7e4a59 iris: Move iris_resolve_conditional_render to the vtable.
It's going to be in genxml code shortly.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-25 18:42:55 +00:00
Kenneth Graunke
6c4c7b600d iris: Refactor genxml macros and inlines into iris_genx_macros.h.
This will let us put the genxml boilerplate in one place, before we
expand genxml to more files shortly.  Like i965/genX_boilerplate.h.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-25 18:42:55 +00:00
Kenneth Graunke
204a3bb816 iris: Make an iris_genx_protos.h header for prototypes.
This lets us specify the prototypes once, instead of cut and pasting
them per generation.  isl uses a similar approach (isl_genX_priv.h).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-25 18:42:55 +00:00
Marek Olšák
068093e84c radeonsi: fix DAL hang due to incorrect DCC offset on Raven
Set the correct relative offset.

Fixes: f8b6c5a "radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support"
2019-07-25 14:09:11 -04:00
Alyssa Rosenzweig
5534fdb7bf panfrost: Compute I/O counts from shader_info
...rather than exposing it in the vendored compiler region.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
4508f43eed panfrost: Don't DIY point size/coord fields
Again, it's in shader_info for us!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
bab4f6c724 panfrost: Use nir_gather_info information about discards
No need to track this ourselves!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
48991c7a1f panfrost: Use NIR helper invocations info
We don't need to guesstimate this ourselves. This will help when we
bringup derivatives.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
fb2fe6e7bc panfrost/sfbd: Flesh out fragment job
We include a zsbuf attachment function based on how the corresponding
MFBD code works, as well as extending cbufs to mipmapped rendering while
we're at it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
e6802af8c3 panfrost: Disable tiled formats on SFBD systems
Just because we don't have the format codes to render to them yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:20 -07:00
Alyssa Rosenzweig
990e24469c panfrost: Move require_sfbd to screen
We'll need it to specialize resource creation by chip.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:20 -07:00
Alyssa Rosenzweig
a9c73e825a panfrost: Reserve, but do not upload, shader padding
Fixes invalid read errors reported by valgrind.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:20 -07:00
Tomeu Vizoso
688d9b4fb7 panfrost/ci: Update kernel to 5.2
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 15:08:44 +02:00
Alyssa Rosenzweig
31c9fcbd0f panfrost: Don't expose some atomic stuff even with dEQP
Fixes dEQP crashes.

Fixes: 2f93ecd654 ("panfrost: Fake CAPs for dEQP-GLES31")

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-24 17:21:12 -07:00
Dave Airlie
16fcbb2eba gallium: fix windows build from params change.
This is why we can't have nice things. I'm sure there's someway
to do this with {0} but I really don't have time for that.

Fixes: 2631fd3b0b ("gallivm: rework lp_build_tgsi_soa to take a struct")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-25 10:02:22 +10:00
Jonathan Marek
bc3b6168ba nir: replace lower_sincos with algebraic opt
This version has less ops for the same precision.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Rob Clark
b4f4768672 gallium/u_transfer_helper: fix assert in RGTC case
Previously we'd hit the unreachable() for uploading RGTC.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-24 21:11:06 +00:00
Jason Ekstrand
c84b8eeeac intel/compiler: Be more conservative about subgroup sizes in GL
The rules for gl_SubgroupSize in Vulkan require that it be a constant
that can be queried through the API.  However, all GL requires is that
it's a uniform.  Instead of always claiming that the subgroup size in
the shader is 32 in GL like we have to do for Vulkan, claim 8 for
geometry stages, the maximum for fragment shaders, and the actual size
for compute.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Qiang Yu
280dfa02fa lima/ppir: fix disassembler temp read/write print
temp read/write use negtive offset, and handle
alignment==1 case.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-07-24 20:39:39 +08:00
Eric Engestrom
e7e31b18d6 gallium+mesa: fix tgsi_semantic array type
Fixes: ed23335a31 ("gallium: use enums in p_shader_tokens.h (v2)")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-24 09:33:29 +01:00
Dave Airlie
2631fd3b0b gallivm: rework lp_build_tgsi_soa to take a struct
The parameters were getting messy and I have to add a few more
for compute shaders, so clean it up before proceeding.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-24 09:20:09 +10:00
Jan Zielinski
3d6cffffcf swr/rasterizer: Fix 3D resource copies.
Ensure constant attributes stay constant with barycentric interpolation.

Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-07-23 21:55:09 +02:00
Jan Zielinski
ec4a5f5e13 swr/rasterizer: Fix return type on SIMD8 version of Clamp and Normalize utility functions
Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-07-23 21:55:09 +02:00
Jan Zielinski
47cdb0ac27 swr/rasterizer: small formatting changes
Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-07-23 21:55:09 +02:00
Jan Zielinski
ccc6b4f96b swr/rasterizer: Adding support for unhandled clipEnable state
Clipping is not correctly handled by the rasterizer - fixing this.

Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-07-23 21:55:09 +02:00
Marek Olšák
264ab6ffcd radeonsi/nir: set tgsi_shader_info::uses_fbfetch for KHR_blend_equation_adv.
This doesn't implement the color buffer load.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:08:37 -04:00
Marek Olšák
45556731b6 tgsi/scan: add uses_fbfetch
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:08:37 -04:00
Marek Olšák
ee858871bd radeonsi: fail if importing a texture with incorrect last_level or samples
v2: don't fail if the texture comes from an incompatible driver.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
2019-07-23 15:08:27 -04:00
Marek Olšák
f8b6c5a1a6 radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:51 -04:00
Marek Olšák
e718f8e713 radeonsi: simplify si_get_input_prim and remove incorrect TODO comment
u_vertices_per_prim(QUADS) is the same as TRIANGLES.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:49 -04:00
Marek Olšák
16392cc3f3 radeonsi/gfx10: fix and enable CLEAR_STATE
it was a driver bug.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:47 -04:00
Marek Olšák
ad642d5b3a radeonsi: stop using info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:46 -04:00
Marek Olšák
6ac2146a98 ac/nir: implement nir_op_pack_{us}norm_2x16
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:44 -04:00
Pierre-Eric Pelloux-Prayer
e9cf8c1d30 u_blitter: add a msaa parameter to util_blitter_clear
Fixes: ea5b7de138 ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-23 14:42:20 -04:00
Pierre-Eric Pelloux-Prayer
d811446e6c u_blitter: enable msaa when dst num samples is > 1
Commit ea5b7de138 broke some piglit tests on radeonsi (Bonaire hardware).
This commit fixes half of the regression by enabling msaa if the dest surface has
more than 1 sample (instead of hardcoding it to false).

Fixes: ea5b7de138 ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-23 14:42:20 -04:00
Guido Günther
85996567f5 kmsro: Extend to include mxsfb-drm
This allows using the LCDIF display controllers (with the mxsfb drm
modesetting driver) along with the Etnaviv render-only drivers. LCDIF is
found on i.MX SoCs.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-23 17:12:10 +00:00
Alyssa Rosenzweig
840b806d64 panfrost/midgard: Allocate registers once (per-screen)
This should save a lot of per-compile time by using the RA the way it's
actually supposed to be used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-23 09:06:21 -07:00
Arnaud Patard
397f9ba69f panfrost: Fix T6XX Support
While testing kmscube with mesa master, it turns out that kmscube is not
working anymore. After bisecting, commit
5a7688fdec is the culprit. A short trial
and error session allowed to find the removed bit of code making kmscube
working again.

This patch adds it back.

Fixes: 5a7688fde ("panfrost: Use 64-bit descriptors globally")

v2: Add comment pointing out this is magic. [Alyssa, trivial]

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-23 08:04:42 -07:00
Alyssa Rosenzweig
83a1d5544a panfrost: Use correct definition for is_t6xx
Rather than anything "early Midgard", limit us specifically to T6XX, as
certain workarounds only apply to genuine T6XX, not T7XX.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-23 08:04:42 -07:00
Michel Dänzer
7499e7362d radeonsi: Allow PIPE_TEXTURE_2D_ARRAY in si_texture_from_handle
Needed for the following st/mesa fix.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-23 16:26:04 +02:00
Alyssa Rosenzweig
2f93ecd654 panfrost: Fake CAPs for dEQP-GLES31
We still have some big ticket items left on GLES 3.0, but it's often
helpful to be able to access higher dEQP levels for debugging features
that just don't quite match a particular API.

Plus, this opens up a whole slew of new features to poke at if boredom
overtakes, ahem.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-23 06:36:48 -07:00
Mark Menzynski
7493fbf032 nvc0/ir: Fix assert accessing null pointer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111167

Signed-off-by: Mark Menzynski <mmenzyns@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann<tobias.klausmann@freenet.de>
2019-07-23 15:08:25 +02:00
Erico Nunes
65e6c42d27 lima/ppir: fix branch codegen register encode
The branch instruction has 6 bits per register operand which allows it
to specify a component in the register.
Fix codegen so that it outputs the right component, otherwise it always
outputs the x component.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-23 08:49:19 +00:00
Erico Nunes
a255b49593 lima/ppir: fix debug logs in regalloc
The macros already prepend "ppir: ", remove them from the actual strings
so it doesn't appear duplicated.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-07-23 08:24:19 +00:00