These are lines of assembly that look valid but are not, and should
raise a parser error but not otherwise crash the assembler or produce
invalid code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
These are valid pairs of hexdumped assembled instructions and the
corresponding disassembly, to be used to regression test both the
assembler and the disassembler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
When we bring up the Valhall compiler in Mesa, we will like to have a
disassembler in native code, so we shouldn't write our disassembler in
Python. Instead, we write a disassembler generator in Python with mako
templates, which will produce a va_disasm_instr entrypoint from the
architecture defined in ISA.xml and valhall.py.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
Logic described in the "Uniform/constant restrictions" section of the
Valhall specification. (You know, my Valhall specification. Is there
another one?)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
This Python script acts as a standalone assembler. It takes Valhall
instructions with Mesa-flavour syntax, parses them, errors out if there
are syntax errors, and writes out an assembled binary if there are not.
It also is available as a programmatic interface for automated testing.
While this attempts to handle syntax errors, it does not check
semantics. It will happily compile programs that fault, provided each
instruction locally 'looks' plausible.
The code itself is quite small, despite supporting most of the known
ISA, because the syntax is regular and the heavylifting is done by
ISA.xml and valhall.py.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
This Python module parses the ISA.xml file added in the previous
commits, extracts all the useful information, and combines it with
extra annotations. In total, it provides a programmatic way to interface
with the Valhall instruction set.
from valhall import instructions, enums
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
This handwritten file is the product of over a hundred hours of
reverse-engineering and represents the sum of what I've learned about
the Valhall architecture. It will be used in the next commits as the
backbone of a Valhall toolchain.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12025>
As the panvk_cmd_alloc_fb_desc function might be called outside a draw,
without a pipeline having been bound to the command buffer.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12019>
In some cases, there will be an open batch because an event operation
has been recorded, or a non-rendering command.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12019>
The logic was incorrectly inverted, although it is correct for Midgard
and in OpenGL.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
This is safer, since it allows the thing being concatenated to itself be
an expande macro, which we'll use as a stopgap to construct tiler jobs
with unified code. It's also a bit more readable, I think.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Midgard calls this nearest but Bifrost calls it point sample. Of the
two, nearest is the standard term, so change the Bifrost XML to use that
name. That way we can share more code constructing samplers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Only fragment and some compute shaders support implicit derivatives.
They're totally meaningless without helper invocations and some
understanding of the dispatch pattern. We've got code to lower
nir_texop_tex in these shader stages to use an explicit derivative of 0
but it was pretty badly broken:
1. It only handled nir_texop_tex, not nir_texop_txb or nir_texop_lod.
2. It didn't take min_lod into account
3. It was conflated with adding a missing LOD parameter to opcodes
which expect one such as nir_texop_txf. While not really a bug,
this does make it way harder to reason about the code.
4. Unless you set a flag (which most drivers don't), it left the
opcode nir_texop_tex instead of nir_texop_txl which it should have
been.
This reworks it to go through roughly the same path as other LOD
lowering only with a constant lod of 0 instead of calling out to
nir_texop_lod. We also get rid of the lower_tex_without_implicit_lod
flag because most drivers set it and those that don't are probably
subtly broken. If someone really wants to get nir_texop_tex in their
vertex shaders, they can write a new patch to add the flag back in.
Fixes: e382890e25 "nir: set default lod to texture opcodes that..."
Fixes: d5ac5d6e83 "nir: Add option to lower tex to txl when..."
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
As discussed with Jason and Connor, this is probably subtly broken on
Mali T720.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Tells you how much use Mali T720 gets that nobody noticed but
Icecream95...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Acked-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12027>
Fixes warnings like the following under clang:
src/panfrost/bifrost/bi_printer.c:599:1: warning: unused function 'bi_widen_as_str' [-Wunused-function]
bi_widen_as_str(enum bi_widen widen)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Fixes the warning caught by clang (why did gcc miss this one?)
../src/panfrost/bifrost/bifrost_compile.h:81:45: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
.lower_bitfield_extract_to_shifts = true,
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
The enums alias. Fixes the following warning under clang:
../src/panfrost/bifrost/bifrost_compile.c:2515:25: warning: implicit conversion from enumeration type 'enum bifrost_texture_fetch' to different enumeration type 'enum bifrost_lod_mode' [-Wenum-conversion]
BIFROST_TEXTURE_FETCH_TEXEL;
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
It's not needed for the standalone compiler. These depend on xf86drm.h which is
not available on other platforms where we might want to build the standalone
compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
We only actually use 4-bits, so we could shrink again. But this by
itself means 1/2 the memory usage for liveness analysis and 1/2 the
copying/alloc/free.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11936>
Gets rid of the silly inheritance everywhere, which has caused _far_
more problems in practice than it has fixed. It was an idea I tried
before the pandemic. It didn't work. I'm finally cleaning it up.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11936>
Otherwise there would be no clause with the dependencies needed for
ATEST set, so the GPU would get stuck.
Not needed on v7, as there shader_wait_dependency in the RSD will wait
for the dependencies before the shader starts.
Explicitly create a NOP instruction, as it is assumed that clauses
have a non-zero count of instructions in various places.
Fixes GPU timeouts in many applications, such as SuperTuxKart and
GZDoom.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11842>
Add the Panfrost pps driver.
v2: Human readable names for counter blocks and use `unreachable`.
v3: Use libpanfrost_perf to collect counter values.
Signed-off-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10215>
Unlike the dependency analysis for the skip bits which is a function of
the data flow graph, the thread termination analysis is dependent on the
actual sequence of instructions. As such, it must be done after
scheduling to be correct in the presence of out-of-order scheduling.
Furthermore it's specified in terms of clauses, not instructions.
Reflecting this in our code gets a nice simplification. As a side effect
this puts extra td flags on subsequent clauses, which matches the DDK's
behaviour. (Maybe td is just a hint?)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10961>
