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65 commits

Author SHA1 Message Date
Chia-I Wu
f825fe8e13 ilo: remove ilo_image_disable_aux() 
Fail resource creation when aux bo allocation fails.
 2015-06-26 13:45:28 +08:00
Chia-I Wu
9871646c13 ilo: remove ilo_buffer 
Since the addition of ilo_vma, it was used only to pad a bo for sampling
engine surfaces.  Replace it entirely with these functions

  ilo_state_surface_buffer_size()
  ilo_state_vertex_buffer_size()
  ilo_state_index_buffer_size()
  ilo_state_sol_buffer_size()
 2015-06-26 13:45:27 +08:00
Chia-I Wu
36d107e92c ilo: introduce ilo_vma 
This cleans up the code a bit and makes ilo_state_vector_resource_renamed()
simpler and more robust.  It also allows a single bo to back mulitple VMAs.
 2015-06-26 13:45:27 +08:00
Chia-I Wu
58f95b332d ilo: align vertex buffer size in buf_create() 
With ilo_format.[ch] moved out of core, the aligning of vertex buffers does
not belong to core anymore.
 2015-06-22 15:18:57 +08:00
Chia-I Wu
9cb0df4b50 ilo: add ilo_image_disable_aux() 
When aux bo allocation fails, ilo_image_disable_aux() should be called to
disable aux buffer.
 2015-06-14 15:43:20 +08:00
Chia-I Wu
1885ac4908 ilo: avoid resource owning in core 
It is up to the users whether to reference count the BOs or not.
 2015-06-14 15:43:20 +08:00
Chia-I Wu
9b705ec32d ilo: add ilo_image_can_enable_aux() 
It replaces ilo_texture_can_enable_hiz().
 2015-05-02 22:14:07 +08:00
Chia-I Wu
f6ca4084c7 ilo: add ilo_image_init_for_imported() 
It replaces ilo_image_update_for_imported_bo() and enables more error
checkings for imported textures.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
c209aa7a8f ilo: improve readability of ilo_image 
Improve docs, rename struct fields, and reorder walk types.  No real changes.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
8ab18262c5 ilo: add ilo_buffer.h to core 
Rename the original ilo_buffer to ilo_buffer_resource to avoid name conflict.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
3afbeb115a ilo: move BOs from ilo_texture to ilo_image 
We want to work with ilo_image instead of ilo_texture in core.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
ac47563cb4 ilo: move ilo_layout.[ch] to core as ilo_image.[ch] 
Move files and s/layout/image/.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
8252765532 ilo: add ilo_format.[ch] to core 
The original ilo_format.[ch] are removed.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
19351af53d ilo: move intel_winsys to ilo_dev_info 
We want to use ilo_dev_info instead of ilo_screen in core.
 2015-05-02 22:14:06 +08:00
Chia-I Wu
bca6c8572f ilo: clarify valid and preferred tilings 
We did it right until the switch to gen_surface_tiling, which has
GEN8_TILING_W.  Generally, GEN8_TILING_W may be valid but not preferred.
 2015-03-07 04:32:39 +08:00
Chia-I Wu
4ddd981e40 ilo: add more convenient intel_bo_{ref,unref}() 
They both check for NULL and intel_bo_ref() returns the referenced bo.  They
replace intel_bo_{reference,unreference}().
 2015-03-06 02:25:03 +08:00
Chia-I Wu
70ef171e91 ilo: add intel_bo_set_tiling() 
Make intel_winsys_alloc_bo() always allocate a linear bo, and add
intel_bo_set_tiling() to set the tiling.  Document the purpose of tiling.
 2015-03-06 02:25:03 +08:00
Chia-I Wu
0ac706535a ilo: replace intel_tiling_mode by gen_surface_tiling 
The former is used by the kernel driver to set up fence registers and to pass
tiling info across processes.  It lacks INTEL_TILING_W, which made our code
less expressive.
 2015-03-06 02:25:03 +08:00
Chia-I Wu
56d2ebb019 ilo: use an accessor for dev->gen 
It should enable us to do specialized builds by making the accessor return a
constant.
 2014-09-12 16:58:30 +08:00
Chia-I Wu
fbb869c1aa ilo: replace domains by reloc flags 
It is simpler and is supported by the kernel.  It cannot be used with
libdrm_intel yet though.
 2014-08-26 14:10:50 +08:00
Chia-I Wu
fb3d506431 ilo: migrate to ilo_layout 
Embed an ilo_layout in ilo_texture, and remove now duplicated members.
 2014-08-19 19:53:37 +08:00
Chia-I Wu
7395432f2e ilo: try unblocking a transfer with a staging bo 
When mapping a busy resource with PIPE_TRANSFER_DISCARD_RANGE or
PIPE_TRANSFER_FLUSH_EXPLICIT, we can avoid blocking by allocating and mapping
a staging bo, and emit pipelined copies at proper places.  Since the staging
bo is never bound to GPU, we give it packed layout to save space.
 2014-07-28 22:57:22 +08:00
Chia-I Wu
0a0e57b070 ilo: enable persistent and coherent transfers 
Enable PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT and reorder caps a bit.
 2014-07-28 22:57:22 +08:00
Chia-I Wu
9d6166880d ilo: check the tilings of imported handles 
Just to be cautious.
 2014-07-24 13:38:51 +08:00
Chia-I Wu
cbc943c43e ilo: clean up resource bo renaming 
s/alloc_bo/rename_bo/ as that is what the functions do.  Simplify bo
allocation and move the complexity to bo renaming.
 2014-07-24 13:21:35 +08:00
Chia-I Wu
cf8c9947a8 ilo: share some code between {tex,buf}_create_bo 
Add resource_get_bo_name() and resource_get_bo_initial_domain() for use by
both functions.
 2014-07-24 10:49:02 +08:00
Chia-I Wu
c1a1a627c4 ilo: use native 3-component vertex formats on GEN7.5+ 
GEN7.5 gains support for those formats natively.
 2014-07-24 09:54:20 +08:00
Chia-I Wu
c25fe88ebf ilo: raise texture size limits 
Report the hardware limits now that max-texture-size piglit test has been
fixed.
 2014-07-15 12:00:15 +08:00
Chia-I Wu
81d7f33e30 ilo: move away from drm_intel_bo_alloc_tiled 
We want to know the exact sizes of the BOs, and the driver has the knowledge
to do so.  Refactoring of the resource allocation code is needed though.
 2014-07-15 12:00:10 +08:00
Chia-I Wu
3e324f99d3 ilo: replace bo alloc flags by initial domains 
The only alloc flag is INTEL_ALLOC_FOR_RENDER, which can as well be expressed
by specifying the initial write domain.  The change makes it obvious that we
failed to set INTEL_ALLOC_FOR_RENDER in several places.
 2014-03-10 16:42:42 +08:00
Chia-I Wu
76713ed5d6 ilo: remove intel_bo_get_size() 
Commit bfa8d21759 uses it to work around a
hardware limitation.  But there are other ways to do it without the need for
intel_bo_get_size().
 2014-03-10 16:42:42 +08:00
Chia-I Wu
e7307fe708 ilo: pipe_texture::usage is not a bitfield 
It happens to work because PIPE_USAGE_STAGING is 0x100.
 2014-02-22 22:45:12 +08:00
Chia-I Wu
f8d19a58dc ilo: set ILO_TEXTURE_CPU_WRITE for imported textures 
Assume the bo has been written by another process, which will trigger a HiZ
resolve.
 2014-02-22 22:45:12 +08:00
Chia-I Wu
7fdab3b201 ilo: disable HiZ for misaligned levels 
We need to disable HiZ for non-8x4 aligned levels, except for level 0, layer
0.  For the very first layer we can adjust Width and Height fields of
3DSTATE_DEPTH_BUFFER to make it aligned.

Specifically, add ILO_TEXTURE_HIZ and set the flag only for properly aligned
levels.  ilo_texture_can_enable_hiz() is updated to check for the flag.

In tex_layout_validate(), align the depth bo to 8x4 so that we can adjust
Width/Height of 3DSTATE_DEPTH_BUFFER without introducing out-of-bound access.

Finally in rectlist blitter, add the ability to adjust 3DSTATE_DEPTH_BUFFER.
 2014-01-14 15:43:20 +08:00
Chia-I Wu
1427c3f79f ilo: decide on hiz first in texture allocation 
Add tex_layout_init_hiz() before tex_layout_init_format() to decide whether
HiZ should be enabled.

On GEN6, because of layer offsetting, HiZ is enabled only when the texture is
non-mipmapped and non-array.  PIPE_USAGE_STAGING is also taken as a hint to
disable HiZ.
 2014-01-14 15:43:20 +08:00
Chia-I Wu
c6605c51de ilo: use HALIGN_4 on GEN7 for depth buffers 
The comment was no longer true since 6642381e75.
 2014-01-14 15:42:53 +08:00
Chia-I Wu
e90e3e39c2 ilo: OOM for HiZ is fatal on GEN6 
On GEN6, HiZ and Separate Stencil Buffer must be enabled at the same time.
 2014-01-14 15:19:41 +08:00
Chia-I Wu
5b1c516080 ilo: fix a HiZ bo leakage 
Dereference the HiZ bo when the texture is destroyed.
 2014-01-14 15:19:41 +08:00
Chia-I Wu
76edf44f9e ilo: enable HiZ 
The support is still early.  Fast depth buffer clear is not enabled yet.

HiZ can be forced off with ILO_DEBUG=nohiz.
 2014-01-08 18:11:36 +08:00
Chia-I Wu
846f70a6ef ilo: rename and add an accessor for texture slices 
Rename ilo_texture::slice_offsets to ilo_texture::slices and add an accessor,
ilo_texture_get_slice().
 2014-01-08 18:11:35 +08:00
Chia-I Wu
546416d495 ilo: add support for HiZ allocation 
Add tex_create_hiz() to create HiZ bo.  It is not really called yet.
 2014-01-08 18:11:35 +08:00
Chia-I Wu
e372819589 ilo: refactor separate stencil allocation 
Move separate stencil allocation code to tex_create_separate_stencil to keep
tex_create sane.
 2014-01-08 18:11:35 +08:00
Axel Davy
e8f9195e5f gallium, intel: Implements new __DRI_IMAGE_USE_LINEAR and PIPE_BIND_LINEAR flags to enforce no tiling. 
Signed-off-by: Axel Davy <axel.davy@ens.fr>
 2013-09-06 15:02:34 -07:00
Chia-I Wu
045bf0db52 ilo: honor surface padding requirements 
The PRM specifies several padding requirements that we failed to honor.
 2013-07-10 12:40:22 +08:00
Chia-I Wu
39226705b7 ilo: update winsys interface 
The motivation is to kill tiling and pitch in struct intel_bo.  That requires
us to make tiling and pitch not queryable, and be passed around as function
parameters.
 2013-06-12 17:46:52 +08:00
Chia-I Wu
cdfb2163c4 ilo: get rid of function tables in winsys 
We are moving toward making struct intel_bo alias drm_intel_bo.  As a first
step, we cannot have function tables.
 2013-06-12 17:46:52 +08:00
Chia-I Wu
3f79188854 ilo: remove unnecessary tex_set_bo/buf_set_bo 
Merge the bodies to tex_create_bo/buf_create_bo respectively.
 2013-06-12 17:46:52 +08:00
Chia-I Wu
6b894e6900 ilo: add support for stencil resources on GEN7+ 
For allocations, we need to support stencil-only and separate stencil
resources.  For mapping, we need to support software tiling and
packing/unpacking for separate stencil resources.
 2013-05-16 18:20:17 +08:00
Chia-I Wu
ca349e0217 ilo: simplify ilo_texture_get_slice_offset() 
Always return a tile-aligned offset.  Also fix for W tiling.
 2013-05-15 15:08:54 +08:00
Chia-I Wu
176ad54c04 ilo: rework ilo_texture 
Use ilo_buffer for buffer resources and ilo_texture for texture resources.  A
major cleanup is necessitated by the separation.
 2013-05-14 16:07:22 +08:00