Commit graph

142 commits

Author SHA1 Message Date
Jason Ekstrand
f82166578f intel/isl: Fix up asserts in calc_phys_level0_extent_sa
The assertion that a format is uncompressed in the multisample layouts
isn't quite right.  What we really want to assert is that the format
supports multisampling which is a bit more complicated query.  We also want
to assert that it has a block size of 1x1 since we do nothing with the
block size in the phys_level0_sa assignment.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-10-03 14:53:01 -07:00
Jason Ekstrand
5637f3f120 intel/isl: Add a format_supports_multisampling helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-10-03 14:53:01 -07:00
Lionel Landwerlin
bc24590f0c intel/i965: make gen_device_info mutable
Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).

This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-23 10:11:59 +03:00
Kenneth Graunke
081f21f29b isl: Finish tiling filtering for Gen6.
Gen6 only has one additional restriction over Gen7+, so we just add it
to the existing gen7 function (which actually covers later gens too).

This should stop FINISHME spew when running GL on Sandybridge.

v2: Fix bytes per block vs. bits per block confusion (Jason) and
    rename function to gen6_filter_tiling (Jason and Chad).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-15 21:21:50 -07:00
Jason Ekstrand
106709db7b Revert "intel/isl: Ignore base_array_layer and array_len for 3D storage..."
This reverts commit 3943888c94.  It turns out
that commit was pretty-much bogus since it breaks binding a 3-D texture as a
2-D storage image.  The correct fix for the Vulkan CTS tests needs to be in
the Vulkan driver itself rather than ISL.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-13 14:45:15 -07:00
Jason Ekstrand
c0b9776cd6 intel/isl: Divide QPitch by 2 for 3-D stencil textures on SKL+
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
00e79cec99 isl/state: Don't set QPitch for GEN4_3D surfaces
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-13 12:40:12 -07:00
Jason Ekstrand
3943888c94 intel/isl: Ignore base_array_layer and array_len for 3D storage surfaces
The time we want to restrict the Z range of a 3-D surface is when rendering
to it.  For storage surfaces, we always want he full range.  However, we
still need to set MinimumArrayElement and RenderTargetViewExtent to
sensible values so we'll just set them to the reasonable defaults we used
before we started respecting the base_array_layer and array_len.

This fixes a bunch of Vulkan CTS regressions caused by 48f195d7c6.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97790
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-13 10:43:21 -07:00
Jason Ekstrand
d038adca0e intel/isl: Add support for RGB formats in X and Y-tiled memory
Normally, using a non-linear tiling format helps improve cache locality by
ensuring that neighboring pixels are usually close-by in memory.  For RGB
formats, this still sort-of holds, but it can also lead to rather terrible
memory access patterns where a single RGB pixel value crosses a tile
boundary and gets split into two pieces in different 4K pages.  It also
makes for some rather awkward calculations because your tile size is no
longer an even multiple of surface element size.  For these reasons, we
chose to simply never create tiled RGB images in the Vulkan driver.

The GL driver, however, is not so kind so we need to support it somehow.  I
briefly toyed with a couple of different schemes but this is the best one I
could come up with.  The fundamental problem is that a tile no longer
contains an integer number of surface elements.  I briefly considered a
couple other options but found them wanting:

 1) Using floats for the logical tile size.  This leads to potential
    rounding error problems.

 2) When presented with a RGB format, just make the tile 3-times as wide.
    This isn't so nice because now our tiles are no longer power-of-two
    size.  Also, it can force the row_pitch to be larger than needed which,
    while not strictly a problem for ISL, causes incompatibility problems
    with the way the GL driver chooses surface pitches.

The chosen method requires that you pay attention and not just assume that
your tile_info is in the units you think it is.  However, it's nice because
it provides a nice "these are the units" declaration in isl_tile_info
itself.  Previously, the tile_info wasn't usable as a stand-alone structure
because you had to also know the format.  It also forces figuring out how
to deal with inconsistencies between tiling and format back to the caller
which is good because the two different consumers of isl_tile_info really
want to deal with it differently:  Computation of the surface size wants
the fewest number of horizontal tiles possible while get_intratile_offset
is far more concerned with things aligning nicely.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Chad Versace <chadversary@chromium.org>
2016-09-12 19:44:05 -07:00
Jason Ekstrand
883086500b intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7
The restriction that Y-tiled surfaces must have valign == 4 only aplies to
render targets but we were applying it universally.  This causes problems
if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this
should be okay because you can't render to that format.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-09-12 19:44:05 -07:00
Jason Ekstrand
8ac99eabb6 intel/isl: Add a helper for getting the size of an interleaved pixel
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
43d25edf78 intel/isl: Fix an assert in get_intratile_offset_sa
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
7ddb21708c intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles
This should be more compact than the enum isl_channel_select[4] that we
were using before.  It's also very convenient because we already had such a
structure in the Vulkan driver we just needed to pull it over.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-09-12 19:42:57 -07:00
Jason Ekstrand
48f195d7c6 intel/isl: Treat 3-D textures as 2-D arrays for rendering
In particular, this means that isl_view::base_array_layer and
isl_view::array_len get applied to 3-D textures but only when rendering.
We were already applying isl_view::base_array_layer for rendering into 3-D
textures so this isn't a huge deviation.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-09-12 16:48:56 -07:00
Topi Pohjolainen
024a39511f isl/gen8+: Allow 1D and 3D auxiliary surfaces
Otherwise once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), assert starts to fire in
piglit case: tex3d. The test uses depth of one which is in fact
supported even now.

v2 (Jason): Allow also 1D case as there is nothing in the specs
            constraining it either.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-12 11:48:29 +03:00
Jason Ekstrand
979d0aca62 intel: Rename brw_get_device_name/info to gen_get_device_name/info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-03 08:23:07 -07:00
Jason Ekstrand
527f371999 intel: s/brw_device_info/gen_device_info/
Generated by:

sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-03 08:23:06 -07:00
Jason Ekstrand
55364ab5b7 intel: Add a new "common" library for more code sharing
The first thing to go in this new library is brw_device_info.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-03 08:23:06 -07:00
Lionel Landwerlin
2dc6930a5a isl: round format alignment to nearest power of 2
A few inline asserts in anv assume alignments are power of 2, but with
formats like R8G8B8 we have odd alignments.

v2: round up to power of 2 (Ilia)

v3: reuse util_next_power_of_two() from gallium/aux/util/u_math.h (Ilia)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-09-01 11:36:09 +01:00
Jason Ekstrand
f4314d06e8 isl/state: Add some asserts about format capabilities
This keeps invalid surface states from leaking through and potentially
hanging the GPU.  We shouldn't actually be hitting this on a regular basis,
but a helpful assert is better than a hang.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-08-29 12:17:34 -07:00
Mauro Rossi
cd18bbeef3 android: intel: Flatten the makefile structure
Android porting of commit bebc1a1 "intel: Flatten the makefile structure"

Automake approach was followed, by moving makefiles a level up,
naming them Android.genxml.mk and Android.isl.mk,
performing the necessary adjustments to the paths,
adding src/intel/Android.mk and fixing mesa top level makefile.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2016-08-29 12:17:34 -07:00
Jason Ekstrand
fb89551047 isl: Allow multisampled array textures
This probably isn't the only thing that needs to be done to get
multisampled array textures working in Vulkan but I think this is all that
ISL really needs and it does fix 8 of the new CTS tests.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-08-26 19:00:02 -07:00
Jason Ekstrand
bebc1a1d99 intel: Flatten the makefile structure
This pulls isl and genxml into a single make file so that they can properly
build in parallel.  This isn't terribly important now as genxml just
generates sources which happens serially first anyway but it will be more
important as we add more stuff to src/intel.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-25 15:29:48 -07:00
Jason Ekstrand
c19fc5e019 isl/tests: Use a longer path for isl.h
The tests assumed that isl would be in the include path but that usually
isn't the case.  Instead, we usually have src/intel and you need to add an
"isl/" prefix.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-25 15:29:47 -07:00
Jason Ekstrand
8bdf605214 intel/isl/gen9: Only use the magic 1D alignment for GEN9_1D surfaces
If the surface has a layout of GEN4_2D then we need to compute a normal 2D
alignment and not use the magic linewar 1D alignment.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-08-25 14:11:15 -07:00
Jason Ekstrand
cda1a5dc0e intel/isl: Pass the dim_layout into choose_alignment_el
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-08-25 14:10:43 -07:00
Jason Ekstrand
f68cfb05fa intel/isl: Use DIM_LAYOUT_GEN4_2D for tiled 1-D surfaces on SKL
The Sky Lake 1D layout is only used if the surface is linear.  For tiled
surfaces such as depth and stencil the old gen4 2D layout is used.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2016-08-25 14:09:44 -07:00
Jason Ekstrand
70bc891c42 isl/formats: Integer formats are not filterable
In ca2a8e5628, we updated the format table to add more formats (most of
which are new on SKL) but accidentally marked some integer formats as
filterable.  You can't filter an integer format.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-23 16:51:34 -07:00
Jason Ekstrand
ca2a8e5628 isl/formats: Update the table with more samplable formats
There were a lot of formats where support was added on Haswell or later but
we never updated the format table.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-23 11:45:24 -07:00
Jason Ekstrand
aba9e25b70 isl/formats: Report ETC as being samplable on Bay Trail
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-23 11:45:24 -07:00
Emil Velikov
d61d259518 isl: automake: use VISIBILITY_CFLAGS to restrict symbol visibility
v2: Add VISIBILITY_CFLAGS to AM_CFLAGS (Ken)

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-08-18 15:06:19 +01:00
Jason Ekstrand
dc880c99b6 isl/state: Only set clear color if aux is used
Otherwise, the clear color will get ignored.  This prevents assertion
errors if clear color is set to something invalid and aux is not used.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
d9df82f2ff isl: Add helpers for creating different types of aux surfaces
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
6155d4ef56 isl/state: Add an assertion for IVB multisample array textures
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
3c75b315e1 isl: Add a #define for DEV_IS_BAYTRAIL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ed432fd681 isl: Add asserts for gen8+ X/YOffset rules
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
560a92c4fd isl: Take the slice0_extent shortcut for interleaved MSAA
The shortcut works just fine for MSAA and the comment even says so.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
1e02611276 isl: Remove duplicate px->sa conversions
In all three cases, we start with width and height taken from
isl_surf::phys_slice0_extent_sa which is already in samples.  There is no
need to do the conversion and doing so gives us an incorrect value.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
ba88a9622d isl: Add functions for computing surface offsets in samples
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
f6c75df083 isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces
The function takes a logical array layer but was assuming it was a physical
array layer.  While we'er here, we also make it not assert-fail on gen9 3-D
surfaces.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
1666d029aa isl/state: Use a valid alignment for 1-D textures
The alignment we use doesn't matter (see the comment) but it should at
least be an alignment we can represent with the enums.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
573f6ffd04 isl: Fix the parameter names for get_intratile_offset
It's been in elements for a while but, for whatever reason, the parameter
names in the header file never got updated.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2016-08-17 14:46:22 -07:00
Jason Ekstrand
21d5c1be6a isl: Add a helper for getting a depth format from an isl_format
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-08 11:13:44 -07:00
Jason Ekstrand
4f282ff67e isl/state: Add support for OffsetX/Y in surface state
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:48 -07:00
Jason Ekstrand
f8984b918a isl: Add support for filling out surface states all the way back to gen4
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:48 -07:00
Jason Ekstrand
815847e2b3 isl: Add an ISL_DEV_IS_G4X macro
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:48 -07:00
Jason Ekstrand
0f6eb5dea0 isl/state: Divide the aux qpitch by 4
The field is in multiples of 4 like regular QPitch.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:47 -07:00
Jason Ekstrand
2c6ca658e7 isl: Fix the bs assertion in isl_tiling_get_info
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 15:53:47 -07:00
Nanley Chery
1fc739d28e Revert "isl: Don't filter tiling flags if a specific tiling bit is set"
This reverts commit 091f1da902 .

Although a user may specify a specfic tiling bit, ISL should still
prevent incompatible tiling/surface combinations.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
2016-07-15 10:35:40 -07:00
Nanley Chery
00caba4152 isl: Fix isl_tiling_is_any_y()
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-15 10:35:40 -07:00