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Author SHA1 Message Date
Kenneth Graunke
f7def1ac1e crocus: Fix a comment about supporting 16x MSAA 
The mask here was already 0xff (8-bits) because only 8x MSAA is
supported, but the comment was copy-pasted from iris which did 16x.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36592>
 2025-08-07 07:30:35 +00:00
Kenneth Graunke
d098b3b973 crocus: Drop 16X MSAA code remnants 
No platforms supported by crocus actually support 16X MSAA, so this is
just copy-pasted from iris without actually offering any benefit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36592>
 2025-08-07 07:30:35 +00:00
Samuel Pitoiset
9765624ed8 radv/ci: fix GPU hang detection regex with recent kernels 
Since July 2024, *ERROR* is no longer printed in dmesg and this caused
GPU hangs to not be detected with recent kernels. Hopefully, this won't
uncover more problems in CI...

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36611>
 2025-08-07 07:08:14 +00:00
Samuel Pitoiset
418a335626 zink/ci: skip spec@arb_fragment_program@fog-modes on RADV 
This test seems to hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36611>
 2025-08-07 07:08:14 +00:00
jglrxavpok
b987ec42ac radv: Avoid calls to strlen when parsing umr output to speed up hang progressing 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36451>
 2025-08-07 06:44:41 +00:00
Samuel Pitoiset
4094706828 radv: invalidate compute/rt descriptors at dispatch time 
Invalidating descriptors at bind time is wrong in a scenario like
trace rays -> dispatch -> trace rays because RT uses compute shaders
and the user SGPRs need to be re-emitted.

Noticed by Konstantin.

Fixes: 40ceece75f ("radv: invalidate compute/rt descriptors at pipeline bind time")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36605>
 2025-08-07 06:26:43 +00:00
Marek Olšák
ba6f731ead glsl: remove gl_shader_compiler_options
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
unused

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:41:40 -04:00
Marek Olšák
10b7f0e95d glsl: move PositionAlwaysInvariant/Precise options to gl_constants 
They are only set for 1 shader stage.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:39:05 -04:00
Marek Olšák
a489fd32f0 st/mesa: replace EmitNoIndirect* with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:39:01 -04:00
Marek Olšák
c57af04c9f glsl: replace LowerPrecisionConstants with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:57 -04:00
Marek Olšák
2fc83bca1f glsl: replace LowerPrecision16BitLoadDst with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:55 -04:00
Marek Olšák
6defdf6518 glsl: replace LowerPrecisionFloat16Uniforms with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:39 -04:00
Marek Olšák
7290cc6eef glsl: replace LowerPrecisionDerivatives with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:35 -04:00
Marek Olšák
3b252cbe92 glsl: replace LowerPrecisionFP16/Int16 with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:33 -04:00
Marek Olšák
7fa7240ae1 glsl: replace LowerBuiltinVariablesXfb with pipe caps 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:02 -04:00
Marek Olšák
0c14420169 glsl: use pipe caps in opt_shader 
do_algebraic doesn't use any options

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36582>
 2025-08-06 17:38:00 -04:00
Connor Abbott
c0884d04d8 tu: Don't keep track of acceleration structure sizes 
We don't actually need to put the size of the AS in the descriptor, as
the blob is doing, because we don't need to rely on bounds checking as
the index is controlled by the driver. The only chance to get a
"garbage" index is if ray query functions are called in the wrong order,
which is already undefined behavior. By just always using the maximum
size, we can stop tracking sizes for VK_EXT_descriptor_buffer where only
the AS address is provided.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36502>
 2025-08-06 21:03:12 +00:00
Marek Olšák
91cee75e63 mesa: stop using inc_mesa in most places that have nothing to do with GL 
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36562>
 2025-08-06 20:35:26 +00:00
Marek Olšák
ebdecb8d45 mesa: remove inc_mapi 
We don't need this to be in include dirs.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36562>
 2025-08-06 20:35:26 +00:00
Marek Olšák
8f2532453c mesa: move src/mapi to src/mesa/glapi 
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36562>
 2025-08-06 20:35:26 +00:00
Eric Engestrom
16e38f6596 lavapipe/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
455b324827 zink+radv/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
54c8cb62e5 broadcom/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
98370280ce radv/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
aaab00d306 radeonsi/ci: document recent flakes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
f6cdb2c620 radv/ci: mark all of dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.* as flaky 
Instead of adding a bunch more, let's just mark the whole group as flaky.

While at it, in the navi21 flakes
`dEQP-VK.ray_tracing_pipeline.pipeline_no_null_shaders_flag.*` already
catches the 4 lines below it, so let's drop them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Eric Engestrom
99eea5cd66 broadcom/ci: skip two more slow CL tests 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36612>
 2025-08-06 16:15:08 +00:00
Job Noorman
64bd81ad51 ir3: allow 2 const srcs in scalar cat2
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
This seems to work just fine.

Totals:
MaxWaves: 2377530 -> 2377514 (-0.00%); split: +0.00%, -0.00%
Instrs: 48221829 -> 48205626 (-0.03%); split: -0.04%, +0.01%
CodeSize: 101944616 -> 101899122 (-0.04%); split: -0.05%, +0.00%
NOPs: 8386509 -> 8386158 (-0.00%); split: -0.04%, +0.04%
MOVs: 1484811 -> 1468853 (-1.07%); split: -1.12%, +0.04%
COVs: 823667 -> 823654 (-0.00%)
Full: 1716521 -> 1716547 (+0.00%); split: -0.00%, +0.00%
(ss): 1113051 -> 1113127 (+0.01%); split: -0.06%, +0.07%
(sy): 552269 -> 552289 (+0.00%); split: -0.05%, +0.05%
(ss)-stall: 4013412 -> 4013046 (-0.01%); split: -0.08%, +0.07%
(sy)-stall: 16739271 -> 16740516 (+0.01%); split: -0.04%, +0.05%
Preamble Instrs: 11509699 -> 11504511 (-0.05%); split: -0.06%, +0.01%
Constlen: 6923600 -> 6923784 (+0.00%)
Last helper: 11692084 -> 11684565 (-0.06%); split: -0.10%, +0.03%
Subgroup size: 12950976 -> 12951168 (+0.00%); split: +0.00%, -0.00%
Cat0: 9241711 -> 9241269 (-0.00%); split: -0.04%, +0.03%
Cat1: 2369298 -> 2353341 (-0.67%); split: -0.70%, +0.03%
Cat2: 17467491 -> 17467666 (+0.00%); split: -0.00%, +0.00%
Cat7: 1637754 -> 1637775 (+0.00%); split: -0.03%, +0.03%

Totals from 14684 (8.92% of 164705) affected shaders:
MaxWaves: 162410 -> 162394 (-0.01%); split: +0.01%, -0.02%
Instrs: 11911204 -> 11895001 (-0.14%); split: -0.16%, +0.03%
CodeSize: 24105958 -> 24060464 (-0.19%); split: -0.21%, +0.02%
NOPs: 2217604 -> 2217253 (-0.02%); split: -0.16%, +0.14%
MOVs: 430148 -> 414190 (-3.71%); split: -3.85%, +0.14%
COVs: 205173 -> 205160 (-0.01%)
Full: 261857 -> 261883 (+0.01%); split: -0.00%, +0.01%
(ss): 305909 -> 305985 (+0.02%); split: -0.24%, +0.26%
(sy): 142011 -> 142031 (+0.01%); split: -0.19%, +0.20%
(ss)-stall: 999663 -> 999297 (-0.04%); split: -0.31%, +0.27%
(sy)-stall: 3848489 -> 3849734 (+0.03%); split: -0.18%, +0.22%
Preamble Instrs: 2569260 -> 2564072 (-0.20%); split: -0.27%, +0.07%
Constlen: 880848 -> 881032 (+0.02%)
Last helper: 4053538 -> 4046019 (-0.19%); split: -0.27%, +0.09%
Subgroup size: 1042368 -> 1042560 (+0.02%); split: +0.05%, -0.03%
Cat0: 2460826 -> 2460384 (-0.02%); split: -0.14%, +0.13%
Cat1: 640559 -> 624602 (-2.49%); split: -2.59%, +0.10%
Cat2: 4299351 -> 4299526 (+0.00%); split: -0.00%, +0.01%
Cat7: 727051 -> 727072 (+0.00%); split: -0.08%, +0.08%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36604>
 2025-08-06 13:56:16 +00:00
Rohan Garg
c978394e00 intel/compiler: use the WA framework when emitting WA 14014595444 
Fixes: d276ad4 "intel/compiler: implement Wa_14014595444 for DG2"
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36262>
 2025-08-06 13:34:28 +00:00
Erik Faye-Lund
fed9bca207 panvk: fix EXT_texture_compression_astc_support 
We can't mix pipe_format and VkFormat values, whoops!

Fixes: ad6e1afe74 ("panvk: add EXT_texture_compression_astc_hdr support")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36601>
 2025-08-06 13:14:24 +00:00
Rob Clark
668a6030fa freedreno/a6xx: Remove old reg builder macros 
Now that there use has been replaced by new cs builders, remove the old
thing.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:25:00 +00:00
Rob Clark
2bff78dcab freedreno/computerator: Convert to new cs builders 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:25:00 +00:00
Rob Clark
5a3607fb3d freedreno/computerator: Convert ubo state to BO 
Build up the descriptor as a normal BO rather than a ringbuffer.

While we are at it, rename to UAV to match the hw.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:59 +00:00
Rob Clark
0162412e36 freedreno/computerator: Split out context restore 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:59 +00:00
Rob Clark
3ddcf8ab92 freedreno/a6xx: Convert gallium to new cs builders 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:59 +00:00
Rob Clark
c4ea8375c4 ir3: Don't count images in num_samp 
The new style reg packers noticed us overflowing SP_xS_CONFIG.num_samp.
Even if we lower image loads to isam, they are using the bindless
descriptors, so no reason to count them here.  Fixes:

  spec@arb_shader_image_load_store@max-images

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:59 +00:00
Rob Clark
4fe255b14d freedreno/a6xx: Rename compute state to cp 
So it doesn't conflict with the new cs builders.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:59 +00:00
Rob Clark
3864d1c209 freedreno/a6xx: Remove compute state user_consts_cmdstream_size 
Unused.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
946bfed6fe freedreno/a6xx: Add new cmdstream builders 
Add new cmdstream builders, including a specialized builder for
CP_CONTEXT_REG_BUNCH.

CRB provides more flexibility than the OUT_REG() pkt4 builder, in not
requiring registers to have consecutive offsets, and faster than
multiple individual pkt4's.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
3b6bf3e3f3 freedreno/a6xx: Make __assert_eq() a nop if !NDEBUG 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
c1aaef71da freedreno/a6xx: Make tex/samp descriptors a normal BO 
This way the descriptor upload is simply memcpy().

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
b17c34326d freedreno/a6xx: Make samp descriptor an array 
So that we can use plain memcpy in the next patch.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
49e5d83d31 freedreno/a6xx: Bake iova's into descriptors 
a6xx+ has long since used FD_BO_NO_HARDPIN, with BO tracking integrated
with resource tracking.  So we don't really need OUT_RELOC() for
building texture descriptors.  We had already dropped that for UVA
descriptors, now cleanup tex descriptors to match.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
dec7022d1a freedreno/a6xx: Separate out blit setup 
With the upcoming NCRB conversion, it is easier if all the setup reg
writes happen in their own scope, so the NCRB builder goes out of scope
and flushes the packet(s).  So re-arrange things a bit so we don't have
to add artificial {}'s

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
5dce5891d2 freedreno/a6xx: Drop orval/shift 
These where always zero for a6xx, and not really supported by the reg
packers.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
2a7f70f697 freedreno: Drop unused emit_const_asserts() param 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
5635f2769f freedreno/registers: Fix RB_A2D_DEST_FLAG_BUFFER_PITCH 
We were using the old-style RB_COLOR_FLAG_BUFFER_PITCH builders for
this.  The new cs builders don't allow that slop.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
a22391632a freedreno/registers: Fix SP_CS_PVT_MEM_BASE type 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
ac5b9f7cd0 freedreno/registers: Rename NCRB 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00
Rob Clark
fc61827688 freedreno/registers: Add some reg64 to pm4 
Some pm4 packets still describe 64b addresses as _HI and _LO reg32.
We'll need the reg64 type="address" (or "waddress") definitions in
order to emit these packets via fd_reg_pair with the new cs builders.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36589>
 2025-08-06 12:24:58 +00:00