Commit graph

22 commits

Author SHA1 Message Date
Marek Olšák
116a05c721 ac: move ac_exp_param.h to ac_nir.h
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
2022-01-05 12:46:31 +00:00
Marek Olšák
d4a1766a5a radeonsi: move the GS copy shader into shader variants
This will allow further optimizations for shader variants that change
GS outputs (affecting the copy shader), and this is mainly about sharing
optimizations with NGG instead of having a totally separate codepath for
legacy GS.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
2022-01-05 12:46:31 +00:00
Marek Olšák
1caa94f2a5 radeonsi: add into the disk cache key whether cached shaders contain LLVM IR
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
2022-01-05 12:46:31 +00:00
Marek Olšák
198ad7e4dc radeonsi: move smoothing to the main shader part to remove 1 live VGPR
The samplemask VGPR that we had to pass to the epilog increased VGPR usage
by 1 for all shaders. Do it in the main function by using the mono key
structure, which causes on-demand compilation and stall, but we'll save
the VGPR.

57794 shaders in 35145 tests
Totals:
SGPRS: 2715856 -> 2716272 (0.02 %)
VGPRS: 1776168 -> 1718432 (-3.25 %)
Spilled SGPRs: 3704 -> 3630 (-2.00 %)
Spilled VGPRs: 1727 -> 1733 (0.35 %)
Private memory VGPRs: 256 -> 256 (0.00 %)
Scratch size: 2008 -> 2016 (0.40 %) dwords per thread
Code Size: 61429584 -> 61393288 (-0.06 %) bytes
Max Waves: 838645 -> 840484 (0.22 %)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
2022-01-05 12:46:31 +00:00
Marek Olšák
054d50904b radeonsi: don't bind the ESGS ring twice, handle the difference in the shader
The other shader is changed to modify the descriptor to get the required
values.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14266>
2022-01-05 12:46:30 +00:00
Marek Olšák
384014bebe radeonsi: apply spi_cu_en to CU_EN
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14122>
2022-01-05 01:36:10 -05:00
Marek Olšák
af9ec3c45d radeonsi: add shader profiles that disable binning
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák
b3b2f97f2e radeonsi: add Wave32 heuristics and shader profiles
This generally works well.

There are new cases that select Wave32, and there are shader profiles
which adjust that.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>
2021-12-11 20:07:35 +00:00
Marek Olšák
cd86f1dc2b radeonsi: rename si_get_shader_wave_size and make it non-inline
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
2021-11-26 11:35:05 +00:00
Marek Olšák
b5665bd46c radeonsi: don't use compute_wave_size directly
It will be removed.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
2021-11-26 11:35:05 +00:00
Marek Olšák
1ef027851d radeonsi: propagate si_shader::wave_size to VGT_SHADER_STAGES
instead of hardcoding them

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
2021-11-26 11:35:05 +00:00
Marek Olšák
8290cae2b7 radeonsi: don't use si_get_wave_size in si_get_ir_cache_key
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
2021-11-26 11:35:05 +00:00
Marek Olšák
d08b09cb7e radeonsi: use si_shader::wave_size
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
2021-11-26 11:35:05 +00:00
Marek Olšák
bc57488936 radeonsi: add si_shader::wave_size because it will vary
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13878>
2021-11-26 11:35:05 +00:00
Marek Olšák
9d7ac70ffb radeonsi: implement shader culling in GS
It already does compaction, so we just need to load vertex positions
and cull. This was easier than expected.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
2021-11-20 00:03:45 +00:00
Marek Olšák
1c5899900d radeonsi: simplify si_get_vs_key_outputs for GS
ngg_culling is always 0 when GS is enabled. This will change in the future.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13829>
2021-11-20 00:03:45 +00:00
Marek Olšák
5a5263d65d radeonsi: unify GFX9_VSGS_NUM_USER_SGPR and GFX9_TESGS_NUM_USER_SGPR
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:46 +00:00
Marek Olšák
61bd8ec043 gallium/radeon: merge BO read/write usage flags with priority flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-29 06:54:21 +00:00
Marek Olšák
cbcdcd42fc radeonsi: enable shader culling on Navi1x consumer SKUs as well
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13393>
2021-10-18 18:08:59 +00:00
Marek Olšák
885f9b3b75 radeonsi: don't memcmp inlined uniform values if uniform inlining is disabled
This uses a C++ template to compute the memcmp size at compile time,
which is important for getting inlined memcmp.

There are 4 different key sizes now:

    GE with inlined uniforms:    68 bytes
    GE without inlined uniforms: 52 bytes
    PS with inlined uniforms:    28 bytes
    PS without inlined uniforms: 12 bytes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13285>
2021-10-16 10:41:51 +00:00
Marek Olšák
8c5a32b5fe radeonsi: split si_shader_key into ps and ge parts to minimize memcmp overhead
ps is for the pixel shader, while ge is for VS, TCS, TES, and GS.

si_shader_key: 68 bytes
si_shader_key_ge: 68 bytes
si_shader_key_ps: 28 bytes

The only notable change is that si_shader_select_with_key is changed
to a C++ template. Other changes are trivial.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13285>
2021-10-16 10:41:51 +00:00
Marek Olšák
385c9e1caf radeonsi: si_state_shaders.c -> cpp
We'll add some templates here.

Why is `extern "C"` not needed for exported functions?

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13285>
2021-10-16 10:41:51 +00:00
Renamed from src/gallium/drivers/radeonsi/si_state_shaders.c (Browse further)