I've recently learned that this is necessary to get
correct results from divergence analysis.
No Fossil DB stats changes on GFX10.3.
Note, when backporting this patch to stable, make sure
the call to nir_convert_to_lcssa is before nir_divergence_analysis,
which may be located in a different place in the stable branch.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23946>
in `a << b` with gcc 13 the shift count c is masked by the
bit count, and a value larger than 32 will result in shifts
by (c & 0x1f), which will add empty instructions if all
color outputs are written and this will eventually
result in an OOM error.
Fixes: 201b46e487
r600/sfn: on R600/R700 write a dummy pixel output if there is a gap
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23945>
When we allocate a new primary sub-command of type
PVR_SUB_CMD_TYPE_TRANSFER we need to make sure the list backing
transfer sub-commands can be shared and managed by both the
secondary and primary sub-command. Do this by always using a
pointer to maintain the list.
Found with:
dEQP-VK.memory.pipeline_barrier.host_write_transfer_src.8192
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reported-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23918>
This defined(_WIN32) is nested in an "#ifdef _WIN32",
so it's duplicated
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23897>
Depth/stencil surfaces cannot be linear but they can be 1D, so they
end up being tile64 when sparse (as we force every sparse resource to
be either tile64 or linear).
According to the "1D surfaces" page from BSpec, our driver treats 1D
surfaces as 2D surfaces with a height of 1 texel, since we don't
enable the corresponding bit from HAS_SLICE_CHICKEN7. And since we
support 2D surfaces, we should also support 1D.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22974>
Just like we avoid it for Tile4, avoid it for Tile64.
We can't easily notice this problem since Tile4 is preferred over
Tile64, but if we patch isl_surf_choose_tiling() to choose Tile64 over
Tile4, then we start getting more than 1600 failures in CI.
These are the two most common error messages:
../src/gallium/drivers/iris/iris_resource.c:2168: get_image_offset_el: Assertion `z0_el == 0 && a0_el == 0' failed.
../src/intel/isl/isl_tiled_memcpy.c:857: linear_to_tiled: Assertion `!"" "unsupported tiling"' failed.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22974>
Add a pass for bounds checking UBOs, SSBOs, and images to implement robustness.
This pass is based on v3d_nir_lower_robust_access.c, with significant
modifications to be appropriate for common code. Notably:
* v3d-isms are removed.
* Stop generating invalid imageSize() instructions for cube maps, this
blows up nir_validate with asahi's lowerings.
* Logic to wrap an intrinsic in an if-statement is extracted in anticipation of
future robustness2 support that will reuse that code path for buffers.
* Misc cleanups to follow modern NIR best practice. This pass is noticeably
shorter than the original v3d version.
For future support of robustness2, I envision the booleans turning into tristate
enums.
There's a few more knobs added for Asahi's benefit. Apple hardware can do
imageLoad and imageStore to non-buffer images (only). There is no support for
image atomics. To handle, Asahi implements software lowering for buffer images
and for image atomics. While the hardware is robust, the software paths are not.
So we would like to use this pass to lower robustness for the software paths but
not the hardware paths.
Or maybe we want a filter callback?
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23895>
I went through the RENDER_SURFACE_STATE docs today and found a number
of fields that are simply gone, marked as "must be zero", or had their
enum meanings change. Update those here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684>
This bit no longer exists and is marked MBZ. I assume that the
optimization is just permanently enabled; this was always a basically
a chicken bit.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23684>
`cl_aligned_packet_length()` expand literals, so use ALIGN_POT to compute it
at compile time.
`v3dv_AllocateMemory()` uses a 64-bit `allocationSize`, so use `align64()`.
`v3d_lower_nir()` uses a 32-bit `shared_size`, so use `align()`.
Extracted out of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23932
for easier review.
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23938>
There are two physical locations, so it makes sense to manage them
separately.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23908>
