4 commits

Author	SHA1	Message	Date
Lionel Landwerlin	ed64eccab0	brw: fix virtual register splitting to not go below physical register size ... Otherwise we can end up generating invalid assembly not following destination/source alignments requirements. Fixes the following tests: dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_4.tan_frag dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_2.tan_frag dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.tan_frag dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_3.tan_frag Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Backport-to: 24.2 Reviewed-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31206>	2024-09-18 23:26:34 +00:00
Romaric Jodin	65c0ef859f	intel/brw: allocate large table in the heap instead of the stack ... When having a large number of virtual register this table can be too large to be allocated on the stack. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30008>	2024-07-03 12:10:28 +00:00
Caio Oliveira	d00329e821	intel/brw: Replace some fs_reg constructors with functions ... Create three helper functions for ATTR, UNIFORM and VGRF creation. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29791>	2024-07-03 02:53:18 +00:00
Caio Oliveira	df013738db	intel/brw: Move virtual GRF opts into their own file ... Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26887>	2024-02-26 20:54:25 +00:00