Commit graph

28940 commits

Author SHA1 Message Date
Rob Clark
f2226acd74 freedreno/ir3: split out ubo info from range
Split out the description of the ubo from the ubo-range.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5526>
2020-06-21 00:52:02 +00:00
Jonathan Marek
df2e54f7d4 freedreno/a6xx: remove unnecessary OVERFLOW_FLAG_REG check
The HW deals with overflow automatically, and presumably does it better
(only disabling for pipes that had overflow, and using the visiblity data
available before the overflow)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5565>
2020-06-20 19:31:48 +00:00
Jonathan Marek
ffecaedf69 freedreno/a6xx: VSC "STRM_ARRAY_PITCH" is "STRM_LIMIT"
This was being set wrong in both freedreno and turnip, and setting it
correctly should avoid hangs when there is overflow.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5565>
2020-06-20 19:31:48 +00:00
Arcady Goldmints-Orlov
04f77595f0 intel/compiler: Always apply sample mask on Vulkan.
With OpenGL, shader writes to the sample mask are ignored when not
rendering to a multisample render target. However, on Vulkan, writes to
the sample mask have still have their effect in that case.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3016

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5156>
2020-06-19 20:24:11 -05:00
Nanley Chery
3915b56e39 iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
2020-06-19 23:32:29 +00:00
Nanley Chery
2305ab6938 iris: Refactor modifier_is_supported for gen12
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
2020-06-19 23:32:29 +00:00
Nanley Chery
c19492bcdb iris: Handle importing aux-enabled surfaces on TGL
Ensure main surfaces are properly 64KB-aligned (as suggested by Jordan)
and map the main surface addresses to aux surface addresses on import.

v2. Add a Bspec quote. (Sagar)
v3. Add a bit more to the Bspec comment. (Ken)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v2)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5420>
2020-06-19 23:32:29 +00:00
Nanley Chery
9dea3e1b47 iris: Use ISL_AUX_USAGE_GEN12_CCS_E on gen12
Makes iris pass a subtest of the fcc-write-after-clear piglit test
(fast-clear tracking across layers 1 -> 0 -> 1) on gen12.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
2020-06-19 22:41:40 +00:00
Nanley Chery
230952c210 iris: Don't support sRGB + Y_TILED_CCS on gen9
Delete some code that would otherwise need updating for
ISL_AUX_USAGE_GEN12_CCS_E.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
2020-06-19 22:41:40 +00:00
Nanley Chery
db5d98cde8 intel: Add ISL_AUX_USAGE_GEN12_CCS_E
Add a new aux usage which more accurately describes the behavior of
CCS_E on gen12. On this platform, writes using the 3D engine are either
compressed or substituted with fast-cleared blocks.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5363>
2020-06-19 22:41:40 +00:00
Nanley Chery
f8961ea086 iris: Disable sRGB fast-clears for non-0/1 values
For texturing and draw calls, HW expects the clear color to be in two
different color spaces after sRGB fast-clears - sRGB in the former and
linear in the latter. Up until now, iris has stored the clear color in
the sRGB color space. Limit the allowable clear colors for sRGB
fast-clears to 0/1 so that both color space requirements are satisfied.

Makes iris pass the sRGB -> sRGB subtest of the fcc-write-after-clear
piglit test on gen9+.

v2:
* Drop iris_context::blend_enables. (Ken)
* Drop some more resolve-related blend-state-tracking code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Nanley Chery
48a3f4c44b iris: Avoid fast-clear with incompatible view
For rendering operations, avoid adding or using fast-cleared blocks if
the render format is incompatible with the clear color interpretation.
Note that the clear color is currently interpreted through the
resource's surface format.

Makes iris pass subtests of the fcc-write-after-clear piglit test:

* UNORM -> SNORM, partial block on gen8+.
* linear -> sRGB, partial block on gen9+.
* UNORM -> SNORM, full block on gen12.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Nanley Chery
fbbf79377b iris: Remove the CCS_D fallback
Remove the CCS_D fallback logic so that iris doesn't attempt to use a
non-existent surface state for some renders. Also, add an assertion to
catch the issue.

The fallback in iris_resource_render_aux_usage can lead to this problem
because it doesn't account for the fact that surface states created from
resources with the Y_TILED_CCS modifier may only have CCS_E or NONE as
aux usages (due to iris_resource_create_with_modifiers).

Without this change, the next commit would have triggered the fallback
and regressed the following tests on gen9:

* dEQP-EGL.functional.wide_color.window_888_colorspace_srgb
* dEQP-EGL.functional.wide_color.window_8888_colorspace_srgb
* dEQP-EGL.functional.wide_color.pbuffer_888_colorspace_srgb
* dEQP-EGL.functional.wide_color.pbuffer_8888_colorspace_srgb

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Nanley Chery
e533232d8c iris: Drop can_fast_clear_color's format parameter
Pull the resource's format from the pipe_resource instead. Makes the
changes in later commits more obvious.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4972>
2020-06-19 21:03:31 +00:00
Kristian H. Kristensen
b1a98a1107 freedreno/a6xx: Set index buffer size to bo size
The number of vertices may be out of bound and if we use it for
computing index buffer size we may get too big a size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5552>
2020-06-19 19:25:34 +00:00
Kristian H. Kristensen
2580e4f921 freedreno/a6xx: Don't write REG_A6XX_RB_SRGB_CNTL in restore
We configure this as part of MRT set up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5552>
2020-06-19 19:25:34 +00:00
Mike Blumenkrantz
292ade3c9d zink: use int assignment for vk int type
this breaks 32bit builds that use -Werror=int-conversion

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5545>
2020-06-19 17:31:51 +00:00
Rob Clark
8f11cc4cad freedreno/ir3: move output_loc to variant
This moves the last bit of important state to be serialized from
ir3_shader to ir3_shader_variant.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Connor Abbott
65660622a1 ir3: Split out variant-specific lowering and optimizations
It seems a lot of the lowerings being run the second time were
unnecessary. In addition, when const_state is moved to the variant,
then it will become impossible to know ahead of time whether a variant
needs additional optimizing, which means that ir3_key_lowers_nir() needs
to go away. The new approach should have the same effect, since it skips
running lowerings that are unnecessary and then skips the opt loop if no
optimizations made progress, but it will work better when we move
ir3_nir_analyze_ubo_ranges() to be after variant creation.

The one maybe controversial thing I did is to make
nir_opt_algebraic_late() always happen during variant lowering. I wanted
to avoid code duplication, and it seems to me that we should push the
_late variants as far back as possible so that later opt_algebraic runs
don't miss out on optimization opportunities.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
91ed8b7fe3 freedreno/ir3: drop shader->num_ubos
The only difference between this and `const_state->num_ubos` was that
the latter is counting # of ubos loaded via `ldg` (based on UBO addrs
in push-consts).  But turns out there isn't really any reason to care.
Instead just add an early return in the one code-path that cares about
the number of `ldg` UBOs.

This gets rid of one more thing we need to move from `ir3_shader` to
`ir3_shader_variant`.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
70fbd48b3a freedreno/ir3: move ubo_state into const_state
As with const_state, this will also need to move into the variant.  To
simplify that, just move it into the const_state itself, since after all
it is related.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
a8b995c055 freedreno/a6xx: defer userconst cmdstream size calculation
The `ubo_state` will also need to move to `ir3_shader_variant`.  But we
can prepare for that and simplify things a bit if we calculate the
cmdstream on first emit, once we already have the appropriate variant.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Rob Clark
bd55533f5b freedreno/ir3: add accessor for const_state
We are going to want to move this back to the variant, and come up with
a different strategy for binning/nonbinning to share the same constant
layout, in order to implement shader-cache support.  (Since then we
can have a mix of dynamically compiled variants and cache hits, so there
is no good place to serialize the const-state.)

To reduce the churn as we re-arrange things, move direct access to the
const-state to a helper fxn.  This patch is the boring churny part.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5508>
2020-06-19 13:16:57 +00:00
Gert Wollny
bddfbfcb56 r600/sfn: Handle memory_barrier
I'm not sure whether this should actually be a barrier accross all
shader processing units, the TGSI code path seems to handle this
only by using GROUP_BARRIER, so let's do the same here.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
34e15cd610 r600/sfn: Take SSBO buffer ID offset into account
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
5aef9ea2a3 r600/sfn: Add support for reading cube image array dim.
The cube array size can't be queried directly, the number of array
elements must be passed via a constant buffer.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
e458683a52 r600/sfn: Add support for image_size
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
249dbcb769 r600/sfn: Add imageio support
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Gert Wollny
b303540c48 r600/sfn: lower image derefs
v2: Signal lowering image derefs by using the CAP

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5206>
2020-06-19 06:58:07 +00:00
Karol Herbst
4bc5110eea nv50/ir/nir: remove image uniform hack
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
2020-06-18 15:15:17 +00:00
Karol Herbst
c0bbca5c23 nv50/ir/nir: handle image atomic inc and dec
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
2020-06-18 15:15:17 +00:00
Karol Herbst
3af27bb7de nv50/ir/nir: move away from image_deref intrinsics
v2: fix lod source of image operation correctly

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5480>
2020-06-18 15:15:17 +00:00
Boyuan Zhang
19983d3d4a radeon/vcn: bump vcn3.0 encode major version to 1
And add quality params for this version

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
2020-06-18 09:58:04 -04:00
Boyuan Zhang
2be131f538 radeon/vcn/enc: Re-write PPS encoding for HEVC
Due to hardware change on VCN3

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
2020-06-18 09:58:03 -04:00
Thong Thai
9d5d4f9eaa radeon/vcn: add vcn 3.0 encode support
Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
2020-06-18 09:58:03 -04:00
Leo Liu
946c5c6b75 radeon/vcn/dec: add db_aligned_height to message buffer
This is required for Sienna

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
2020-06-18 09:58:03 -04:00
Leo Liu
384195b041 radeon/vcn: add Sienna to use internal register offset
And re-group them explicitly

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
2020-06-18 09:58:03 -04:00
Leo Liu
909037b557 radeon/vcn: reset the decode flags from message buffer
This flag was never used by VCN previously, and now
it's used for feature that is not applied to us.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
2020-06-18 09:58:03 -04:00
Rob Clark
c6632c087d freedreno/a6xx: set .MERGEREGS based on variant
Also set HALFREGFOOTPRINT, since in the non-mergeregs case this will be
non-zero.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
2020-06-18 02:46:28 +00:00
Rob Clark
c052087038 freedreno/ir3: re-work assembler API
Just pass thru the variant, since it has everything we need.  And
will be needed in the next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5458>
2020-06-18 02:46:28 +00:00
Jonathan Marek
d53dc6c376 freedreno/fdl6: rework layout code a bit (reduce linear align to 64 bytes)
Reduce linear alignment, and rework the layout code a bit.

This rework has a side effect of also increasing the alignment on linear
levels of tiled (non-ubwc) cpp=1 and cpp=2 layouts. Since we should be
UBWC for those cases anyway, its not a big loss.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5013>
2020-06-18 02:26:43 +00:00
Jonathan Marek
3a9ab3b6e9 freedreno/a6xx: FETCHSIZE is PITCHALIGN
"FETCHSIZE" is actually a "minimum pitch" or "pitchalign" value that's
relevant for mipmaps. The 0 value means 64-bytes. Understanding this allows
some simplifications and will make it possible to use less alignment on
linear formats.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5013>
2020-06-18 02:26:43 +00:00
Eric Engestrom
9ca2a4e6fc freedreno: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
2020-06-18 02:09:56 +00:00
Eric Engestrom
bd5cf70d3d etnaviv: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
2020-06-18 02:09:56 +00:00
Eric Engestrom
e0e9c2486d iris: replace all dup() with os_dupfd_cloexec()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
2020-06-18 02:09:56 +00:00
Eric Engestrom
4a8085d67c replace all F_DUPFD_CLOEXEC with os_dupfd_cloexec()
All squashed into a single commit because it shouldn't have any
behaviour change, except that it might work now on platforms where it
was broken because F_DUPFD_CLOEXEC is not supported but FD_CLOEXEC is.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5369>
2020-06-18 02:09:56 +00:00
Mike Blumenkrantz
e8ad52f7b0 zink: enable xfb extension in screen creation
switch around the feature enabling as well since extensions need the related
feature to also be enabled in order to function

fixes mesa/mesa#2868

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5163>
2020-06-17 20:42:01 +00:00
Mike Blumenkrantz
e5e657768c zink: switch to passing VkPhysicalDeviceFeatures2 in VkDeviceCreateInfo
extensions need to have their feature structs passed in pNext to be enabled,
so switch to using the feature struct here in preparation for that

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5163>
2020-06-17 20:42:01 +00:00
Mike Blumenkrantz
1983609212 zink: set PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED and remove POS special casing
this cap creates a different varying output which remains constant to be
emitted by xfb, allowing us to drop the special-casing code in ntv

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5163>
2020-06-17 20:42:01 +00:00
Mike Blumenkrantz
37778fcd9a zink: implement transform feedback support to finish off opengl 3.0
this adds:
* context hooks for gallium stream output methods
* handling for xfb-related queries
* barrier management for pausing and resuming xfb

loosely based on patches originally written by Dave Airlie <airlied@redhat.com>

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5163>
2020-06-17 20:42:01 +00:00