4 commits

Author	SHA1	Message	Date
Sagar Ghuge	2ea041e04a	intel/compiler: Pack texture LOD and offset to a single 32-bit value ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>	2024-02-27 00:22:46 +00:00
Sagar Ghuge	9b37b3ba73	intel/compiler: Pack LOD/bias and array index on TG4 messages ... Bspec: 56996 Programming note: When doing cube arrays on gather4_l and gather4_b with SIMD16 or SIMD32 the AI parameters is combined with the LOD/bias parameter on the 9 LSBs. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>	2024-02-27 00:22:46 +00:00
Sagar Ghuge	d4ce848476	intel/compiler: Trim vector properly till array index ... This fixes the off-by one mistake, we want to trim the vector till the array index not till the coordinates last component. v2: (Ian) - Use tex->coord_component - 1 in nir_trim_vector Fixes: 73a3257968 ("intel/compiler: Add texture operation lowering pass") Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>	2024-02-27 00:22:46 +00:00
Caio Oliveira	d8f9a05f32	intel/compiler: Rename the passes and files related to intel_nir.h ... Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>	2024-02-16 22:35:05 +00:00

Renamed from src/intel/compiler/brw_nir_lower_texture.c (Browse further)