Commit graph

87454 commits

Author SHA1 Message Date
Matt Turner
deae25ce37 i965: Use separate enums for register vs immediate types
The hardware encodings often mean different things depending on whether
the source is an immediate.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
8815b9677f i965: Reorder brw_reg_type enum values
These vaguely corresponded to the hardware encodings, but that is purely
historical at this point. Reorder them so we stop making things "almost
work" when mixing enums.

The ordering has been closen so that no enum value is the same as a
compatible hardware encoding.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
ce6b8627d8 i965: Validate destination restrictions with vector immediates
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
1d79c828d8 i965: Don't let raw-move check be tricked by immediate vector types
UB and B type encodings are the same as UV and VF. Noticed when writing
the following patch.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
48aa6ecb87 i965: Only change type of 0.0f to VF if destination stride == 1
The destination stride must be equivalent to a dword if VF is used.

Also, since the only compaction table entires with "i:vf" have the
destination as "r:f" specifically check that the destination is of type
float.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
56a676eed2 i965: Remove CONT/BREAK from instruction compaction test
These cannot be compacted. A similar mistake was fixed in commit
90eaf01616

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
3d661e6062 i965: Test instruction compaction on all supported Gens
Note that there's no point in testing on G45, since its compaction is
the same as Gen5. Same logic applies to Gen7 variants and low-power
parts.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
9ff7d9b853 i965: Silence signed/unsigned comparison warning
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
eac89911e5 i965: Move compaction "prepass" into brw_eu_compact.c
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner
17641f6388 i965: Mark src inst pointer const in compaction code
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Dave Airlie
b3f87b87f6 vulkan: import 1.0.59 headers and xml.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-22 07:00:50 +10:00
Rob Herring
4734bfc02a Android: Fix LLVM duplicated symbols linking for N and M
Both statically linking libLLVMCore and dynamically linking libLLVM causes
duplicated symbols in gallium_dri.so and it fails to dlopen. We don't
really need to link libLLVMCore, but just need generated headers to be
built first. Dynamically linking to libLLVM instead is enough to do
that. Thanks to Qiang Yu for finding the root cause.

With this change, we can align all versions and just have libLLVM as a
shared lib dependency.

This also requires changes in the M and N versions of LLVM to export the
include paths for libLLVM. AOSP master is okay.

Fixes: 26aee6f4d5 ("Android: rework LLVM build support")
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-08-21 10:46:21 -05:00
Leo Liu
03b89547b7 st/va: add MJPEG for config
To enable MJPEG HW decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
5608f44271 st/va: reallocate surface with YUYV stream
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
2ebc530ca3 st/va: detect MJPEG format from bitstream
To find if the format is supported YUYV by sampling factor which
is embedded from bitstream. So we could use this info for buffer
reallocation on the correct format.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
7319ff8787 radeon/uvd: add YUYV format support for target buffer
Make chroma plane optional for YUYV support

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
c4061bb5fa st/va: reallocate surface when interlaced
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
fceb52a230 radeon/video: MJPEG not support stacked video buffers
So we have to detect it for reallocation of de-interlaced buffers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
e50ee6d4d5 st/va: make surface allocate functions more usefully
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
130d1f456b radeon/uvd: reconstruct MJPEG bitstream
The current tier 1 mjpeg firmware only supports at the bitstream
level, the later tier 2 support will be at the buffers level with
newer hardware.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
ef099e6799 st/va: add slice parameter handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
8e9175744e st/va: add huffman table handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
93577e6081 st/va: add iq matrix handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
535b3c2363 st/va: add picture parameter handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
41f17eb5f0 st/va: add handles for MJPEG Buffers
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
38b9686df0 st/va: create decoder for MJPEG format
Mjpeg doesn't need reference

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
0a59477372 st/va: add MJPEG picture to context
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
15f3335577 radeon/video: add MJPEG support
v2: add ASIC and Kernel version check

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
3fe713ce3d radeon/uvd: add MJPEG support
There is no need of dpb buffer for mjpeg codec

v2: check dpb_size instead of format

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
b26cfdaebd radeon/uvd: add MJPEG stream type
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
4ac38ac3de vl: add MJPEG picture description
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
11ccb56e9f vl: add MJPEG profile and format
v2: move util video change to here

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu
2b1eacabfa radeon/uvd: get the target buffer pitch correct for different format
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Samuel Pitoiset
2843c5d15c radeonsi: update non-resident bindless descriptors if needed
Only resident bindless descriptors are currently updated and
re-uploaded, this makes sure that the non-resident ones are
also updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-21 15:23:56 +02:00
Louis-Francis Ratté-Boulianne
498814a3ca dri3: Move up fourcc utility function
It will be needed in next patches.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-08-21 12:55:54 +01:00
Daniel Stone
85ef0215dd egl: Add dma_buf_import_modifiers for glvnd
Make sure we advertise the new entrypoints to libglvnd's EGL dispatch.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reported-by: Emmanuel Gil Peyrot <emmanuel.peyrot@collabora.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101982
Fixes: 4c412293d0 ("egl: advertise EGL_EXT_image_dma_buf_import_modifiers")
2017-08-21 12:13:50 +01:00
Topi Pohjolainen
393ec1a507 intel/blorp: Adjust intra-tile x when faking rgb with red-only
v2 (Jason): Adjust directly in surf_fake_rgb_with_red()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-08-21 09:55:08 +03:00
Dave Airlie
b040f51b61 ac/nir: fixup layer/viewport export for GFX9.
GFX9 moved where the viewport index export goes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-08-21 04:26:37 +01:00
Jason Ekstrand
c366943ebf i965/bufmgr: s/BO_ALLOC_FOR_RENDER/BO_ALLOC_BUSY/
"Alloc for render" is a terrible name for a flag because it means
basically nothing.  What the flag really does is allocate a busy BO
which someone theorized at one point in time would be more efficient if
you're planning to immediately render to it.  If the flag really means
"alloc a busy BO" we should just call it that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-20 20:14:49 -07:00
Jason Ekstrand
cadcd89278 i965/tex: Change the flags type on create_for_teximage
This matches the actual function declaration.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-20 20:14:49 -07:00
Christoph Haag
87556a650a mesa: only copy requested compressed teximage cubemap faces
This is analogous to commit 2259b11 which only fixed the regular case

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102308
Signed-off-by: Christoph Haag <haagch+mesadev@frickel.club>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2017-08-20 17:01:48 -04:00
Jason Ekstrand
f24cf82d6d i965/tex: Don't pass samples to miptree_create_for_teximage
In 76e2f390f9, when Topi switched num_samples from 0 to 1 for
single-sampled, he accidentally switched the last parameter in the call
to miptree_create_for_teximage from 0 to 1 thinking it was num_samples
when it was actually layout_flags.  Switching from 0 to 1 added the
MIPTREE_LAYOUT_ACCELERATED_UPLOAD flag which causes us to allocate a
busy BO instead of an idle one.  This caused the subsequent CPU upload
to consistently stall.  The end result was a 15% performance drop in the
SynMark v7 DrvRes microbenchmark.  This restores the old behavior and
fixes the performance regression.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes: 76e2f390f9
Bugzilla: https://bugs.freedesktop.org/102260
Cc: mesa-stable@lists.freedesktop.org
2017-08-19 15:39:12 -07:00
Kenneth Graunke
6f8a577ed2 anv: Use ISL for emitting null surface states.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:48 -07:00
Kenneth Graunke
5ae983c85b i965: Use ISL for emitting null surface states.
We handle the Sandybridge multisampled 2D surface hack here, rather
than in ISL, because it requires allocating a BO, and is kind of messy.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:46 -07:00
Kenneth Graunke
5db9757bd7 isl: Add a null surface fill function.
ISL already offers functions to fill out most kinds of SURFACE_STATE,
so why not handle null surfaces too?

Null surfaces are simple, so we can just take the dimensions, rather
than an entirte fill structure.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:36 -07:00
Kenneth Graunke
288621b1b7 i965: Remove tabs in intel_batchbuffer.c.
Our coding style is to use spaces.  Some of this was also messed up
during my bufmgr import series.

(Trivial, just whitespace changes.)
2017-08-18 23:51:56 -07:00
Jason Ekstrand
61d2f3f1c2 i965/miptree: Return NONE from texture_aux_usage when fully resolved
This little optimization improves the performance of SynMark v7
TexFilterTri by almost 10% on Sky Lake GT4 among other improvements.
We've been doing it for some time but somehow it got dropped during
the miptree refactoring.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/102258
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-18 17:31:02 -07:00
Jason Ekstrand
d5e217dbfd i965: Stop looking at NewDriverState when emitting 3DSTATE_URB
Looking at NewDriverState is not safe in general.  The state atom system
is set up to ensure that new bits that get added to NewDriverState get
accumulated into the set of bits used when emitting atoms but it doesn't
go the other way.  If we read NewDriverState, we may not get the full
picture because the per-pipeline state (3D or compute) does not get
added to NewDriverState before state emit is done.  It's especially
dangerous to do this from BLORP (either explicitly or implicitly when
BLORP calls gen7_upload_urb) because that does not happen during one of
the normal state upload paths.

This commit solves the problem by whacking all of the per-shader-stage
URB sizes to zero whenever we change the total URB size.  We still have
to flag BRW_NEW_URB_SIZE to ensure that the gen7_urb atom triggers but
the actual decision in gen7_upload_urb can now be based entirely on URB
sizes rather than on state atoms.  This also makes BLORP correct because
it just asks for a new URB config whenever the vsize is too small and so
any change to the total URB size will trigger blorp to re-emit as well
because 0 < vs_entry_size.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/102289
Cc: mesa-stable@lists.freedesktop.org
2017-08-18 17:30:55 -07:00
Kenneth Graunke
bc56dfbf3f i965: Mark all EGLimages as non-coherent.
EGLimages are shared with external users, and we don't know what they're
going to do with them.  They might scan them out.  They might access
them in a way that doesn't work with our explicit clflushing.

It's safest to simply mark them non-coherent.

Chris Wilson caught this problem and wrote a similar (though less
aggressive) patch to solve it; the miptree code has since undergone
a lot of refactoring so I had to rewrite it.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-08-18 16:28:13 -07:00
Eric Anholt
a727e03360 broadcom/genxml: Add V3D 3.3 packet definitions.
This will be used by the new vc5 gallium driver, and a future Vulkan
driver.
2017-08-18 12:54:13 -07:00