We need to add a JM barrier after the memset(0) COMPUTE job if we want
to ensure the header reset happens before any texturing from this texture
in subsequent COMPUTE/VERTEX jobs.
Fixes: c95f899305 ("panvk: add a meta command for transitioning image layout
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
cmd_clear_afbc_metadata() might be called before any other job, and it's
assuming dispatch_precomp() doesn't fail in that case. We could
explicitly open the batch in cmd_clear_afbc_metadata(), but checking for
cur_batch==NULL and opening a new batch seems to be okay too, and it
allows us to not special case for v7 in cmd_clear_afbc_metadata().
Fixes: c95f899305 ("panvk: add a meta command for transitioning image layout")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
There seems to be cases where we end up with a depth/stencil preload,
with no draw associated to it, so let's make sure we preload in that
case, otherwise we will write invalid data back.
Fixes: 0bc3502ca3 ("panvk: Implement a custom FB preload logic")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
In panvk_vX_cmd_meta.c, panvk_plane_index() is passed the bit position
instead of an aspect in a couple places.
Fixes: c95f899305 ("panvk: add a meta command for transitioning image layout")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
Commit 33eff977f6 ("panvk: Use pan_image_test_props() to do our
modifier check") removed the checks that are already done by
pan_image_test_props() from panvk_image_can_use_afbc(), but it didn't
account for the fact panvk_image_can_use_afbc() is also used to
report suboptimal setup when HOST_TRANSFER is set.
Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 33eff977f6 ("panvk: Use pan_image_test_props() to do our modifier check")
Closes: https://gitlab.freedesktop.org/panfrost/mesa/-/issues/204
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37158>
It seems like everything involving the multithreaded ES2 tests is prone
to flaking out with a segfault. Just wildcard the lot until we can
bottom out what's actually going on.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37305>
The current code assumes 2M and 4k pages. If an allocation request
is larger than 2M, allocation will be aligned to 2M, otherwise to
4k.
The new code is informed by pgsize_bitmap. The allocation is
aligned to a particular page boundary, if the request is at least
as large as that page boundary. Note that given
pgsize_bitmap = PGSIZE_4K | PGSIZE_2M
2M requests will now be aligned to a 2M boundary, rather than 4k,
which is the case with the current code.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37288>
This function returns the page size of the VM that we're using. The
GPU page size might be different from what the host process uses.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37288>
pgsize_bitmap specifies the page sizes supported by the VM.
Aligning the mappings to huge-r pages can increase access perf.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37288>
When the host process is 32-bit, size_t can not express all of the
device address space. Note that there's still a lot of code that
uses size_t for device sizes remaining. Cleaning that up is left
for future MRs.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37288>
Blending should work properly those days.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37271>
This is wrong for SNORM and this is handled by nir_lower_blend.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37271>
The change to the implicit subpass barriers uncovered a CTS bug that is
now hitting CI. The issue is fixed in vulkan-cts-1.4.2.1, but CI is
currently on vulkan-cts-1.4.1.1.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36985>
On Valhall, we can end up with a lot of convertions for 8-bit and 16-bit
values.
However, since Valhall, we have access to a lot more swizzles on widen
sources.
The idea of this pass is to propagate replicate swizzle usages to
simplify things.
We do not attempt to propagate MKVEC.v2i16 as it is already handled by
bi_lower_swizzle.
This changes the following:
9 = V2S8_TO_V2S16 !7.b0
11 = IADD.v2s16 !9.h00, u4
88 = MKVEC.v2i8 11.b0, u256.b0, u256
13 = IMUL.v4i8 !88.b0, 8.b0
14 = V2S8_TO_V2S16 !13.b0
15 = IADD.v2s16 14.h00, !11.h00
89 = MKVEC.v2i8 !15.b0, u256.b0, u256
17 = IMUL.v4i8 !89.b0, !8.b0
Into this:
11 = IADD.v2s16 !7.b0, u4
13 = IMUL.v4i8 11.b0, 8.b0
15 = IADD.v2s16 13.b0, !11.h00
17 = IMUL.v4i8 !15.b0, !8.b0
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37167>
We are going to do more things here that will likely benefit from
possibly running multiple time.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37167>
It alwways comes in through the create flags now.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36957>
This moves the bit into vk_image.h and handles it automatically in
vk_image_view_init() so drivers don't have to.
This also means that Meta is now hitting the driver_internal path for
all its images so we need to do the same format fixups there that we
sould normally do on the !driver_internal path. We don't want to do
them unconditionally because v3dv and other drivers override
depth/stencil color formats and we don't want to break that.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36957>
When spilling registers on Valhall we are careful to leave the TLS
pointer aligned on 16 byte boundaries (so as to avoid accesses
crossing those boundaries). However, within the spill code we don't
need to have 16 byte alignment for spills of 32 or 64 bit values.
In the common case where most spills are 32 bits, we can save nearly
75% of the memory used by just aligning to 32 bit boundaries.
Reviewed-by: Aksel Hjerpbakk <aksel.hjerpbakk@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36676>
We were testing some conditions in the wrong order, so spilled
registers were being printed as if they were uniforms. This is
incorrect, but only subtly so, and lead to confusion.
Fixes: 6c64ad934f ("panfrost: spill registers in SSA form")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37092>
The intention of the code was to allow PHI values to be propagated
if they were in registers (as opposed to in memory). As written though
values were never propagated. I think this typo was due to some
debug code that wasn't removed properly.
Fixes: 6c64ad934f ("panfrost: spill registers in SSA form")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37092>
On v11+, all small integers instruction variants are gone, however we
can now use widen on src0 just fine.
That mean we can get ride of mid conversion by relying on swizzle
instead while respecting signess of the inner instruction.
This helps a little bit on clpeak with panvk+clvk, shader-db is also
happy:
Totals:
Instrs: 109541 -> 109354 (-0.17%)
CodeSize: 1110528 -> 1108864 (-0.15%)
Estimated normalized CVT cycles: 667.609375 -> 664.5625 (-0.46%)
Totals from 17 (2.12% of 803) affected shaders:
Instrs: 13637 -> 13450 (-1.37%)
CodeSize: 112256 -> 110592 (-1.48%)
Estimated normalized CVT cycles: 100.203125 -> 97.15625 (-3.04%)
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37125>
We already do this many places, let's add the missing ones for the core
Vulkan versions.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37136>
Similar to what we do for features here, let's group things a bit more
consistently.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37136>
The feature bits have been added a bit willy-nilly, let's clean that up
a bit.
The general structure here is that if something is part of a specific
Vulkan version, we list the feature under there in the order they are
defined in the version-specific structure. If not, we list it under
an extension. Clean up so each version is in it's own block.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37136>
These two properties reports how the interaction between MSAA coverage
and occlusion queries works. We need to report the correct value here,
otherwise applications might misbehave.
Fixes: 5ee3c10d1e ("panvk: advertise vulkan 1.4 on v10+")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37136>
Seems this just works, so let's enable it.
Unlike maintenance 4 through 8, VK_KHR_maintenance9 doesn't have a hard
dependency on Vulkan 1.1, and can also be supported on Bifrost.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36987>
Techically speaking, this isn't needed. Allocating a new BO should zero
out the memory in the first place.
But let's do this anyway, because that assumption might change at some
point. Besides, this adds fairly little overhead, and happens in a
non-critical code-path.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36987>
In theory, we should be able to support
separateDepthStencilAttachmentAccess, but in practice this occasionally
fails tests. So let's disable it for now, and deal with that feature
down the line.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36987>
nir_opt_if was unable to optimize some ifs later on so let's get ride of
them as soon as we generated them for simplicity.
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37030>
Instead of allocating constants to the FAU entries on a
first-come-first-serve basis, it would be more efficient to put the most
frequently used constants in the FAU so we save the most amount of ADD_IMM
to push constants into registers.
This commit does so using a simple pass before the main constant lowering
pass.
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>
Following on the previous commit, this commit adds support for selecting
and reporting constants to pull from the FAU instead of loading them
into registers first with ADD_IMM. This is beneficial because we can then
use them as a source directly and save ourselves one instruction to move
them into the register first.
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>
This commit sets up support for constants that should be pushed into
FAU entries after the ones we already push (sysvals, push constants).
The next commit will make the compiler actually find and report the
constants that should be pushed.
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36872>
It turns out that the `occlusion_query.syncobj` is used to set
state that later code relies on, and setting it to NULL causes
some Vulkan CTS tests to fail. Instead, we should explicitly check
for the mode being `MALI_OCCLUSION_MODE_DISABLED` to avoid using
an invalid `ptr` field.
Fixes: 24c692c981 ("panvk: fix a NULL pointer dereference in occlusion queries")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36794>
This way we report the *actual* tilebuffer sizes rather than reporting
twice the amount and then correcting for it later on. The distinction
really only matters on V4 and V6 GPUs, but let's get it correct.
This shouln't have any functional changes, it just makes it easier to
reason about what each GPU supports.
While we're at it, correct the typo in the comment about what gens
supports disabling pipelining. It's *not* supported on V6.
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35755>
When using formats with less than 32-bits per pixel, we pad the
tile-buffer to a multiple of 32-bits so we can store additional bits
used by dithering.
Account for this when computing the max MSAA setting.
Fixes: 329568b5eb ("panfrost: add color-attachment and msaa helpers")
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35755>
Make sure that depth and color buffers have the same number of
samples. This *should* be guaranteed by the higher levels, but
in the case of a bug we want to notice quickly (and in fact
such a bug has bitten us, see panfrost/mesa/issue#200).
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36876>
This avoids having to hardcode the proxy in the traces `download-url` or
jobs setting `PIGLIT_REPLAY_EXTRA_ARGS` and accidentally overriding the
default args when the author meant to append.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36955>
Without this, I get failures in the following CTS test:
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
Fixes: 05006c21dd ("panvk/utrace: Alloc utrace copy buf from userspace heap")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36980>
Right now, we store the last VkDeviceMemory object bound to an image in
panvk_image::mem, but this doesn't work for disjoint images where the mem
object can differ on each plane.
Move panvk_image::mem to panvk_image_plane::mem and prefix the offset
field with mem_, so it's clear the offset refers to the mem object.
Note this should only fix host copy on disjoint images, since the GPU
address was already properly set at bind time.
Fixes: 1cd61ee948 ("panvk: implement VK_EXT_host_image_copy for linear color images")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36926>
Commit c11f47481a ("panvk: stop CPU mapping all index buffers on JM")
stopped mapping the buffer objects on v9-, but it forgot to remove
panvk_buffer::host_ptr and panvk_cmd_graphics_state::host_addr.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36934>
Based on the previous commit, we can also remove the dynamic allocation
for command memory from the submit path and use the new pool instead.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36609>
