3 commits

Author	SHA1	Message	Date
Caio Oliveira	d59bd421a2	intel/brw: Rename fs_inst to brw_inst ... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33114>	2025-01-31 00:57:21 +00:00
Caio Oliveira	650ec7169d	intel/brw: Add SHADER_OPCODE_SEND_GATHER ... Starting in Xe3, there's a variant of SEND that take the register numbers from the ARF scalar register, and don't require them to be contiguous. The new opcode added here represents that kind of SEND. To make the original sources still reachable, we keep them around during the IR, just ignoring them at generator time. This allow software scoreboard to properly reason the dependencies without trying to decode the contents of ARF scalar register being used. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Lionel Landwerlin <None> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32410>	2025-01-30 04:43:58 +00:00
Caio Oliveira	634daf2827	intel/brw: Rename brw_fs_validate to brw_validate ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32843>	2025-01-13 23:56:22 +00:00

Renamed from src/intel/compiler/brw_fs_validate.cpp (Browse further)