Keep the support in gen_sort_xml.py to allow it still convert
old MRs into the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
And change the gen_sort_xml.py script to default to the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Change code to temporarily support both the start/end old format and the
dword/bits new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Add a `--bits-format` argument to normalize the output to either of the
formats described below. For now, defaults to the old format.
The documentation in PRMs and BSpec describe the fields with the dword
and the bit range. Using the same convention makes easier to spot
issues.
Old format:
```
<field name="Disable SLM Read Merge Optimization" start="38" end="38" type="bool" />
<field name="Pixel Async Compute Thread Limit" start="39" end="41" type="uint" prefix="PACTL">
```
New format:
```
<field name="Disable SLM Read Merge Optimization" dword="1" bits="6:6" type="bool" />
<field name="Pixel Async Compute Thread Limit" dword="1" bits="9:7" type="uint" prefix="PACTL">
```
For Groups, we store the dword and if needed a offset_bits, in case
a group starts in a non-aligned position. Size and count for groups are
not changed.
Do this first for gen_sort_tags.py in case is convenient to have for the
stable tree to convert future patches from the new back into the old
format. Later patches will add support to the rest of the code.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Avoid noise when changing to the new GenXML field format -- which would
try to also sort it. Also add this file to be checked as part of tests.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
so we can gather_info later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36265>
Correctly/optimally using nir_opt_varyings directly is pretty tricky. For GL, we
have all the right logic in the GLSL linker. for VK, we don't want to duplicate
this dance in every driver. Wrap it all up in a nir_opt_varyings_bulk helper
that operates on an entire pipeline of nir_shader's, following the GLSL linker's
logic. This is suitable for Vulkan drivers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36265>
Despite appearances, the current vk_pipeline implementation fails to link any
shaders, unless GPL is used or the link_geom_stages option is set (which no
drivers do). Notably monolithic pipelines don't get linked.
This patch attempts to fix our linking issues. Monolithic pipelines now get
linked, GPL optimized pipelines do too. GPL fast link is still not linked.
Geometry stages are now always linked because - despite the option - I think all
hardware wants this. Apps love writing random dead varyings for literally no
reason, which isn't free even on NVIDIA. This removes the option, effectively
setting it for all drivers, which in retrospect is the right decision.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36265>
vkd3d-proton sets this to the size of the backing memory which means we
will overwrite random buffer contents when performing acceleration
structure copies.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36197>
Sampling with layer!=0 from a non arrayed descriptor should return 0 and
sampling without an explicit array layer from and arrayed descriptor
should sample the first layer.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36197>
block->imm_dom is NULL for unreachable phis, so the dominance checks would crash.
These blocks should be removed by nir_opt_dead_cf, so don't bother optimizing
them here.
Fixes: 60776f87c3 ("nir/opt_remove_phis: rematerialize constants")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35935>
We avoid adding unconditionally the 64-bytes padding to all usages
of the vulkan memory allocations. The readahead padding is only added
for buffers/images with USAGE_TRANSFER_SRC_BIT usage enabled as this
is enough for having a full vk-cts without reported MMU TFU errors.
vk-cts doesn't exercise the added image memory requirements codepath to
handle this readahead. This is because the required 64-bytes image
alignments for images with flag VK_IMAGE_USAGE_TRANSFER_SRC_BIT.
But the alignment didn't cover when the image is already aligned to
64-bytes at the end of the memory page.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36159>
Most of it is tracking stuff that is ending synchronously anyways.
For example, in emit_barrier_insert_waits, cs_sync64_wait is sync and
therefore there is no need to defer the timestamp write on any SBs.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36161>
This is so that in subsequent commits the wait mask can be:
- set by the caller
- not provided at all -> synchronous ts write
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36161>
