When both inputs are denorms, the bcsel picks the integer min/max result,
which does not flush denorms and therefore might return the wrong result.
Fixes OpenCL fmin/fmax on asahi.
Fixes: d238d766c6 ("nir: add lower_fminmax_signed_zero")
Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41386>
numFds could be no less than 1 based on the number of plane(s) and
metadata(optional) fd in a gralloc buf handle. and amdgpu backend
of gralloc should make sure all plane bufs within same dma_buf fd
but different offset.
handle->data[0] already indicates dma_buf fd of plane(s) well.
Signed-off-by: Ken Xue <Ken.Xue@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41879>
This change updates the configuration to fix some
regressions with the fpu64 emulation.
Note: The r600 has a single precision fma op code which
breaks the fpu64 emulation if used as nir_op_ffma (It
likely returns a double).
This change was tested on palm and barts.
Fixes: aeea2e7c1f ("nir: add fmad_or_ffma helpers and use it in lower_double_ops")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41781>
The Mesa PowerVR driver is Vulkan only, and Zink is used solely for
APIs implemented by Gallium.
Change the driver name to "zink" if the device node's driver is
"powervr".
Backport-to: 26.1
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41737>
This reverts commit adf18abb40.
Some setups rely on matching kmsro for render nodes (e.g. clients to
wlroot-based compositors).
Backport-to: 26.1
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41737>
brw_nir_lower_deferred_urb_writes assumes that constant offsets will be
properly folded. In brw itself we call the big optimization loop which
takes care of this, but jay doesn't do that in-between.
At any rate, nir_lower_io generates a lot of address math that really
ought to get cleaned up, so it seems like a good point to call it here.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
I meant to add these together, not put a random semicolon in the middle
of the expression which meant the offset got tossed on the floor.
Fixes: 6fbe201a12 ("brw: Convert VS/TES/GS outputs to URB intrinsics.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
We now calculate it when emitting push input loads at the NIR level,
rather than in the backend.
v2: Fix missing interaction with legacy tesslevel remapping
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
We were seeing if the start of the load was within the push range,
rather than the entire load. (We could also split loads, but that
seems needlessly complex.)
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
Calculate the end of our read as a byte offset and divide by the 32B
unit of URB reads. We were calculating 1 byte beyond the start offset
and dividing by 8 (the number of 4 byte DWords in 1 unit of URB read).
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
SIMD4x2 mode is only supported by elk which anv doesn't use. iris
doesn't check this. Eventually we should probably just demote the
dispatch_mode field to the stages that still need it.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41821>
This works by splitting lp_descriptor into image, sampler and buffer
descriptor types. The lavapipe side needs to be adjusted to handle
descriptor set layouts with varying descriptor sizes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39496>
This is what LowerBoundedU32Array is doing internally and it's unlikely
faster to have all these extra cases. This also gets rid of a bunch of
transmute(), which is always nice. It does mean a small copy in the
case of large SSARefs but those should be uncommon.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41462>
This is a generalization of NAK's SSAValue and SSAValueArray structs.
But instead of depending on NAK's bespoke invariants, this depends on
something far simpler: A lower bound on the u32. As long as you can
guarantee that the maximum array length is strictly less than the
minimum U32 value, we can pull the same trick as NAK and generalize it
into a LowerBoundedU32Array type.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41462>
Now that every caller goes through brw_to_binary(), brw_generator has
a single user (brw_to_binary.cpp itself). Move the class definition
into that .cpp inside an anonymous namespace and delete the header,
so it can no longer leak into other translation units.
No functional change.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41413>
