Commit graph

5 commits

Author SHA1 Message Date
Matt Turner
c17c47207b mesa: Remove force_s3tc_enable driconf variable
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-02 19:41:22 -07:00
Nicolai Hähnle
7a62f8621a radeonsi: allow out-of-order rasterization in commutative blending cases
We do not enable this by default for additive blending, since it slightly
breaks OpenGL invariance guarantees due to non-determinism.

Still, there may be some applications can benefit from white-listing
via the radeonsi_commutative_blend_add drirc setting without any real
visible artifacts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-09-18 11:25:20 +02:00
Nicolai Hähnle
8c56c45cd4 radeonsi: add drirc option "radeonsi_assume_no_z_fights"
This option enables a performance optimization where typical non-blending
draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE
chips).

This optimization can lead to incorrect results when an applications
renders multiple objects with the same Z value at the same pixel, so we
will never enable it by default. But there may be applications that could
benefit from white-listing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-09-18 11:25:19 +02:00
Nicolai Hähnle
53485c2d0e radeonsi: add enable_sisched driconf option
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-02 09:50:59 +02:00
Nicolai Hähnle
601093f95d xmlconfig: move into src/util
v2: attempt to fix Android build (Emil)

v3: add missing include path

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2017-07-31 15:38:41 +02:00