The option creates a buffer where each bit stores whether the
corresponding 4096 byte memory section has been allocated. The helper
radv_build_is_valid_va allows for querying the validity of addresses
inside a nir shader which can be useful for debugging.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34392>
The first part is for copying "normal" push constant values to the
upload space in the preprocess buffer. The second part is only for
updating the push constants set for DGC.
This will allow us to remove using the pipeline layout in the DGC
shader.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36777>
This only updates the inlined push constants set for DGC and doesn't
need the pipeline layout if the index is computed differently.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36777>
This is actually not needed because the base pipeline/shader is
required to be bind before preprocess()/execute() are called. Also,
the push constant layout must be similar between all pipelines/shaders
in the same IES.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36777>
These information need to consider that pipelines/shaders in the same
IES struct might slightly differ. They will be used to determine the
preprocess buffer size in a better way.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
I completely missed that it's required for the application to pass the
IES struct in vkGetGeneratedCommandsMemoryRequirementsEXT. Also any
changes to the IES struct requires to call it again.
This will allow us to do more optimizations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
layout->push_constant_mask is only the DGC push constant mask (ie. the
tokens that are specified), but with IES all push constants are emitted
from the DGC shader. So it should be the total range of push constant.
This used to work by luck due to the preprocess buffer alignment.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36753>
DRM syncobjs always let you wait repeatedly on them, so we can set the
flag in the core instead of having each driver override it once they try
to enable the emulated timeline semaphores.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36563>
Drivers that doesn't support direct unaligned dispatches, they can use
the shader creation flag to lower unaligned dispatches.
Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36245>
This disables HiZ on-demand when both depth/stencil are enabled and
depth writes are enabled to prevent potential issues.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
This fixes an issue with Hellblade Senua's Sacrifice because
RADV_PERFTEST_RT_WAVE_64 is set using drirc, but if two devices are
created RADV_PERFTEST flags might differ.
The proposed solution is to filter out unused RADV_PERFTEST flags for
the winsys.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36727>
GFX12 seems to behave slightly differently. Setting these bits to TRUE
causes zero-area triangles to not pass the primitive clipping stage.
So, the actual number of primitives output by the primitive clipping
stage was wrong.
After digging a lot, it seems PAL doesn't set these bits either on
GFX12.
CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36670>
It's always better if init/finish come in pairs.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36646>
It was just a dummy wrapper around the runtime struct. We do, however,
have to keep at least the Create/Update entrypoints because RADV has to
do some patching for video encode. Since we're keeping Create, we keep
Destroy as well.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36646>
This also allows us to simplify the interface to
vk_video_session_parameters_create().
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36646>
These are never created on the stack or deep inside other objects so it
makes sense to use create/destroy instead of init/finish.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36646>
OPTIMAL is actually linear for VCN4 and older, so this needs to check
the surface flags instead.
Fixes: 2d06b43292 ("radv: Enable tiling for video images on VCN5")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36669>
radeon_cmdbuf is too low level for stuff like tracked registers and
buffered registers on GFX11+.
This commit introduces radv_cmd_stream which is defined like:
struct radv_cmd_stream {
struct radeon_cmdbuf *b;
// TODO: add tracked regs
// TODO: add buffered regs
};
It will be much easier/cleaner to implement tracked/buffered registers
with this new structure.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36314>
