Commit graph

127608 commits

Author SHA1 Message Date
Marcin Ślusarz
88b935bb0c mesa: fix formatting of messages printed using _mesa_log
... on BOTH _WIN32 and !_WIN32

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6443>
2020-08-25 09:07:51 +00:00
Lionel Landwerlin
fd10cb8cfc anv: fix transform feedback surface size
Non multiple 4 sizes are causing issue in particular < 4.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3450
Fixes: 36ee2fd61c ("anv: Implement the basic form of VK_EXT_transform_feedback")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6430>
2020-08-25 10:13:52 +03:00
Woody Chow
5e4d69ec78 st/mesa: Fix EGLImageTargetTexture2D for GL_TEXTURE_2D
Before this change, internalFormat was defaulted to GL_RGBA (
unsized internal format). Therefore, subsequent glTexSubImage2D
call with type != GL_UNSIGNED_BYTE, GL_UNSIGNED_SHORT_4_4_4_4 or
GL_UNSIGNED_SHORT_5_5_5_1 would give GL_INVALID_OPERATION.

This fixes

android.graphics.cts.BitmapColorSpaceTest#test16bitHardware
android.graphics.cts.ImageDecoderTest#testDecodeBitmap*
android.graphics.cts.BitmapTest#testNdkFormatsHardware

in CtsGraphicsTestCases

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6382>
2020-08-25 02:10:15 +00:00
Vinson Lee
855afe0144 meson: Fix lmsensors warning message.
Fixes: 138c003d22 ("meson: deprecated 'true' and 'false' in combo options for 'enabled' and 'disabled'")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6397>
2020-08-24 17:37:26 -07:00
Eric Anholt
c6861b9f75 freedreno: Drop UNIFORM_BUFFER_OFFSET_ALIGNMENT to 32
This is the value exposed by the a3xx-a4xx drivers according to an
official Adreno OpenGL ES Developer guide I found, and also a report I saw
for a5xx while googling.  Fixes renderdoc replay of a manhattan31 trace
captured on a Pixel 3a.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6416>
2020-08-24 23:23:05 +00:00
Daniel Schürmann
a79dad950b nir,amd: remove trinary_minmax opcodes
These consist of the variations nir_op_{i|u|f}{min|max|med}3 which are either
lowered in the backend (LLVM) anyway or can be recombined by the backend (ACO).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6421>
2020-08-24 20:56:11 +00:00
Rob Clark
1fa43a4a8e freedreno: handle case of shadowing current render target
If you have a sequence where there is a single buffer associated with
the current render target, and then you end up shadowing it on the 3d
pipe (u_blitter), because of how we swap the new shadow and rsc before
the back-blit, you could end up confusing things into thinking that
the blitters framebuffer state is the same as the current framebuffer
state.

Re-organizing the sequence to swap after the blit is complicated when
also having to deal with CPU memcpy blit path, and the batch/rsc
accounting.  So instead just detect this case and flush if we need to.

Fixes:
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_clear
dEQP-GLES31.functional.stencil_texturing.render.depth24_stencil8_draw

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6434>
2020-08-24 20:15:23 +00:00
Rob Clark
743ad7bf6b freedreno: add debug helper to dump buffers
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6434>
2020-08-24 20:15:23 +00:00
Rob Clark
6f9bb6c26a freedreno/a6xx: refactor debug logging
Break it out into a helper fxn, and cleanup the copy/pasta.  Also, add
something so we can tell when src and/or dst are UBWC.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6434>
2020-08-24 20:15:23 +00:00
Marek Olšák
440aab95c3 gallium/tgsi: add helper tgsi_get_interp_mode
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
2519472845 st/mesa: handle lowered IO in st_nir_assign_vs_in_locations
There are piglit failures without this.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
2424485fb4 st/mesa: don't generate NIR for ARB_vp/fp if NIR is not preferred
Fixes: 5d0630e504 "st/mesa: call prog_to_nir sooner for ARB_fp"
Fixes: a3de63fbb3 "st/mesa: don't generate VS TGSI if NIR is enabled"

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
493fdcf446 st/mesa: don't pass NIR to draw module if IO is lowered
The draw module can't handle it.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
484a60d547 nir: generate lowered IO in nir_lower_passthrough_edgeflags
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
7980f3e519 nir: add interpolation qualifiers for color sysvals into shader_info
needed by radeonsi

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
4d36dceeab nir: add shader_info::io_lowered
This will drive decisions in many NIR passes and st/mesa.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
844167d100 nir: properly identify texcoords for lowered IO in nir_lower_drawpixels
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
2b1ef5df4e nir: print IO semantics (v2)
v2: print GS streams readably

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
01ab308edc nir: update IO semantics in nir_io_add_const_offset_to_base
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
17af07024d nir: gather all IO info from IO intrinsics
nir_io_add_const_offset_to_base will shrink num_slots, so it's better to
call it before nir_shader_gather_info.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Marek Olšák
502abfce7f nir: save IO semantics in lowered IO intrinsics
This enables drivers and utils to get all IO information from intrinsics,
so that they don't have to walk the complex types of NIR variables to find
out other information about IO intrinsics.

NIR in/out variables can be removed after nir_lower_io. We could remove
the variables in the pass, but for now I just decided to remove
the variables in radeonsi before shaders are returned to st/mesa.
(st/mesa just needs adjustments to work without NIR in/out variables)

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6442>
2020-08-24 19:07:18 +00:00
Lionel Landwerlin
ec1fa1d51f intel/perf: fix raw query kernel metric selection
The raw query is meant to be used with MDAPI [1]. When using this
metric without this library, we usually selected the TestOa metric to
provide some default sensible values (instead of undefined).
Historically this TestOa metric lived in the kernel at ID=1. We
removed all metrics from the kernel in kernel commit 9aba9c188da136
("drm/i915/perf: remove generated code").

This fixes the Mesa code to use a valid metric set ID (1 could work
some of the time, but not guaranteed).

[1] : https://github.com/intel/metrics-discovery

v2: Store fallback metric at init time

v3: Drop TestOa lookout

v4: Skip the existing queries (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
CC: <mesa-stable@lists.freedesktop.org>
Tested-by: Marcin Ślusarz <marcin.slusarz@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6438>
2020-08-24 18:52:23 +00:00
Lionel Landwerlin
f1da3bb3d5 intel/perf: store query symbol name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6438>
2020-08-24 18:52:23 +00:00
Eric Anholt
a9019d14ae nir/load_store_vectorizer: Clean up unit test swizzle assertions.
They're hard to write and read, so put together a little helper to clean
up both the code and the gtest output on failure.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6431>
2020-08-24 17:16:05 +00:00
Eric Anholt
2b25240993 freedreno/ir3: Replace our custom vec4 UBO intrinsic with the shared lowering.
This gets us fewer comparisons in the shaders that we need to optimize
back out, and reduces backend code.

total instructions in shared programs: 11547270 -> 7219930 (-37.48%)
total full in shared programs: 334268 -> 319602 (-4.39%)

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
2020-08-24 09:53:36 -07:00
Eric Anholt
73616598bd nir: Add a lowering pass for backends wanting load_ubo with vec4 offsets.
This is very common for backends -- r600, freedreno, and nir_to_tgsi all
needed versions of it.  Make a common intrinsic to use for it with a
shared, slightly-tuned-from-ir3 lowering pass.

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
2020-08-24 09:53:35 -07:00
Eric Anholt
d84a16e481 nir: Add nir_[iu]shr_imm and nir_udiv_imm helpers and use them.
I was doing math manually in a lowering pass for converting a division to
a ushr, and this will let the pass be expressed more naturally.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
2020-08-24 09:53:17 -07:00
Eric Anholt
e78b887f76 nir: Make the nir_builder *_imm helpers consistently handle bit size.
We always want to demote the y to the bit size of the ssa def, but also
want to sanity check that our input and our masking is big enough.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6378>
2020-08-24 09:53:09 -07:00
Timur Kristóf
f820dde201 aco: Fix convert_to_SDWA when instruction has 3 operands.
Previously, when the instruction had 3 operands, this would cause
possible corruption because of writing to sdwa->sel[2].
This was noticed thanks to GCC 10's -Wstringop-overflow warning.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6436>
2020-08-24 15:55:14 +02:00
Timur Kristóf
0d194a70c6 aco: Fix unused variable warning by adding ASSERTED.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6436>
2020-08-24 15:55:06 +02:00
Alyssa Rosenzweig
089bc22de5 r300: Use util_blend_factor_uses_dest
v2: Fix missing { and #include (trivial)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
2020-08-24 11:42:35 +00:00
Alyssa Rosenzweig
7a776f43d2 si: Use util_blend_factor_uses_dest
Driver-local copy is redundant.

v2: Fix missing #include (trivial)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
2020-08-24 11:42:35 +00:00
Alyssa Rosenzweig
e055463459 gallium: Add util_blend_uses_dest helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
2020-08-24 11:42:34 +00:00
Alyssa Rosenzweig
e05930511b gallium: Add util_blend_factor_uses_dest helper
Drivers may be able to optimize cases where blending is enabled but the
destination colour is not used. This helps detect that case.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6407>
2020-08-24 11:42:34 +00:00
Samuel Pitoiset
48a910d1f9 radv: use the trap handler to detect faulty shaders/instructions
It should reliably report the faulty shader but the faulty instruction
is inacurate, especially for memory violations because it's reported
when the addr is processed. It will be improved by emitting more
wait-states.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
8e97a61cfb radv: enable the trap handler and configure the shader exceptions
When TRAP_PRESENT is not enabled, all traps and exceptions are ignored.
Only EXCP_EN.mem_viol is currently supported because the other
exceptions have to be tested/validated first.

EXCP_EN.mem_viol is used to detect any sort of invalid memory
access like VM fault. When a memory violation is reported, the
hw jumps to the trap handler.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
af3230e39e radv: add initial trap handler support with RADV_TRAP_HANDLER=1
A trap handler is used to handle shader exceptions like memory
violations, divide by zero etc. The trap handler shader code will
help to identify the faulty shader/instruction and to report
more information for better debugging.

This has only been tested on GFX8, though it should work on GFX6-GFX7.
It seems we need a different implemenation for GFX9+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
8fd2f5c16d radv: add a small interface for creating the trap handler shader
Similar to the GS copy shader except that NIR is unused because
the shader is written directly using ACO IR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
a0814a873d aco: skip unnecessary compiler pass for the trap handler program
The shader is written by hands with assigned registers, so most of
the pass are unnecessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
9c46e6fca3 aco: add a helper for building a trap handler shader
It's way easier to write a trap handler shader using ACO IR
instead of writing disassembly by hand + clrxasm + copy&paste.

This trap handler is quite simple for now, it just loads a
buffer descriptor from the TMA BO, it saves ttmp0-1 which
contain various info about the faulty instruction, and it
stores some hw registers about the wave/trap status.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
a6146aa598 aco: validate that SMEM operands can use fixed registers
To fix a validation error when loading the scalar tma buffer
descriptor because it's not a temp but a fixed reg (tma_lo/tma_hi).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
baa9268eb6 aco: add TBA/TMA/TTMP0-11 physical registers definitions
The TBA/TMA scalar registers are only available on GFX6-GFX8.

On GFX9+, TBA/TMA addr are stored in hardware registers and
the number of TTMP scalar registers is thus increased by 4.
Just keep in mind that tba_lo is actually ttmp0. Best would
be to support ttmp registers in RA but that's more complicated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
7e493e510b amd/registers: add some SQ_WAVE_* register definitions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Samuel Pitoiset
3aa71a61dd amd/registers: add missing TBA registers on GFX6-GFX8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6384>
2020-08-24 11:08:24 +00:00
Erik Faye-Lund
5e841e8b4f nir: add iabs-lowering code
Microsoft's DXIL is based on LLVM, which doesn't have an integer ABS
opcode, but instead needs it lowered to NEG + MAX. We need to do this
with an option, to prevent an already existing optimization rule from
undoing this.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5211>
2020-08-24 10:02:47 +00:00
Eric Engestrom
9e5e3be412 egl: drop invalid shebang
This file exports a variable that is then used in a python script,
but it can never be executed by itself, so having a shebang here
makes no sense.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6166>
2020-08-22 11:47:42 +00:00
Jason Ekstrand
32dc71b23a clover: Call clang with -O0 for the SPIR-V path
SPIRV-LLVM-Translator isn't really built for handling optimized LLVM IR.
It tends to fall over when, for instance, an optimization generates an
i96 type which isn't legal in SPIR-V.  Pass -O0 to avoid these cases.
See https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/203.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6432>
2020-08-22 00:27:07 +00:00
Jason Ekstrand
e3e45e2456 clover/spirv: Don't call llvm::regularizeLlvmForSpirv
writeSpirv() already takes care of that, and calling it twice seems to
duplicate functions and cause problems when processing execution modes.

Fixes: 2043c5f37c "clover/llvm: Add functions for compiling from..."
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6306>
2020-08-21 23:18:08 +00:00
Jason Ekstrand
c84e2784eb intel/nir: Allow splitting a single load into up to 32 loads
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
2020-08-21 22:49:54 +00:00
Jason Ekstrand
febe762246 intel/fs: Fix an assert in load_scratch
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6405>
2020-08-21 22:49:54 +00:00