fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-24 23:38:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
47158 commits 66 branches 936 tags 996 MiB
Commit graph

7693 commits

Author SHA1 Message Date
Christoph Bumiller
bb0482a55b nv50/ir: import SM4 converter 2011-10-21 23:00:40 +02:00
Christoph Bumiller
d988361ead nouveau,nvc0: fix/improve handling of multiple constant buffers 2011-10-21 23:00:40 +02:00
Christoph Bumiller
28271fd00d nvc0: add support for linear and buffer textures and RTs 2011-10-21 23:00:40 +02:00
Christoph Bumiller
73ea0e7fd4 nvc0: add support for clip distance shader outputs 2011-10-21 23:00:40 +02:00
Christoph Bumiller
b4ecef4b1b nvc0: handle more query types 2011-10-21 23:00:40 +02:00
Christoph Bumiller
3cc1dd5b80 nvc0: fix location of the PrimitiveID output 2011-10-21 23:00:39 +02:00
Christoph Bumiller
3637537a1f nvc0: prevent VERTEXID/INSTANCEID from consuming input slots 2011-10-21 23:00:39 +02:00
Christoph Bumiller
44c23e9052 nvc0: fixes for program tessellation parameters 2011-10-21 23:00:39 +02:00
Christoph Bumiller
8bc3a87f40 nv50,nvc0: reset per-instance state for inactive vertex elements 2011-10-21 23:00:39 +02:00
Christoph Bumiller
6994b57a50 nv50,nvc0: reset base element in draw_arrays 
It affects VERTEX_BUFFER_FIRST,COUNT submission, too.
 2011-10-21 23:00:39 +02:00
Christoph Bumiller
8828004e67 nvc0: apply first_layer offset to all resources with array_size 
Makes CUBE arrays work with d3d1x.
 2011-10-21 23:00:39 +02:00
Christoph Bumiller
840bc04b43 nvc0: emit state to allow GP to select the RT layer 2011-10-21 23:00:39 +02:00
Christoph Bumiller
6db14200eb nvc0: validate GP samplers, textures 2011-10-21 23:00:39 +02:00
Christoph Bumiller
e104bb9f92 nvc0: fix clear_render_target/depth_stencil region 
In all 3 dimensions (now clearing all layers too).
 2011-10-21 23:00:39 +02:00
Christoph Bumiller
ff583a47ee nvc0: fix assertion that immediate array buffer fits 2011-10-21 23:00:39 +02:00
Christoph Bumiller
52c8c52b22 nv50/ir: use RDSV to fetch FrontFacing before lowering 2011-10-21 23:00:39 +02:00
Christoph Bumiller
9c930639d9 nv50/ir: fix textureGrad with offsets and in non-FPs 2011-10-21 23:00:39 +02:00
Christoph Bumiller
0e4e0ca6df nv50/ir: add wrap mode for shift operations 
D3D1x specifies that only the low 5 bit of the shift are used.
 2011-10-21 23:00:39 +02:00
Christoph Bumiller
974102c7c2 nv50/ir: initialize RelocInfo to 0 2011-10-21 23:00:38 +02:00
Christoph Bumiller
7920c3c192 nvc0/ir: fix emission of cvt when register and type size differ 2011-10-21 23:00:38 +02:00
Christoph Bumiller
37a08ddce5 nv50/ir: fix argument count for CUBE_ARRAY texture target 2011-10-21 23:00:38 +02:00
Christoph Bumiller
2ec5c8feb3 nvc0/ir: GP emit address must end up in $r0 2011-10-21 23:00:38 +02:00
Christoph Bumiller
30cb66cd74 nvc0/ir: TXQ requires different lowering from normal TEX 2011-10-21 23:00:38 +02:00
Christoph Bumiller
6b27f14680 nv50/ir: initialize default prog_info values for GP,TP 2011-10-21 23:00:38 +02:00
Christoph Bumiller
63ca1abcc4 nv50/ir: fix memory value equality check 2011-10-21 23:00:38 +02:00
Christoph Bumiller
e3a3844e8d nv50/ir: fix leak in removal of graph root 2011-10-21 23:00:38 +02:00
Christoph Bumiller
c43b2f6a30 nvc0/ir: handle levelZero modifier in TEX emission 2011-10-21 23:00:37 +02:00
Christoph Bumiller
b5f2c0505f nvc0/ir: fix lowering of DIV F32 2011-10-21 23:00:37 +02:00
Christoph Bumiller
3fc2818f2b nvc0/ir: fix xy confusion typo in readTessCoord 2011-10-21 23:00:37 +02:00
Marek Olšák
7a3bbd3d5d r600g: cleanup r600_reset_blittable_to_compressed 2011-10-21 03:34:54 +02:00
Marek Olšák
a04f8c3612 r300g: don't return NULL in resource_from_handle if the resource is too small 
The DDX may allocate a buffer with a too small size.
Instead of failing, let's pretend everything's alright.

Such bugs should be fixed in the DDX, of course.

NOTE: This is a candidate for the stable branches.
 2011-10-20 23:37:22 +02:00
Christoph Bumiller
1f4f0c41db softpipe: implement/fix TIMESTAMP queries 2011-10-20 18:03:49 +02:00
Brian Paul
9a8791c889 softpipe: remove unused vars in softpipe_clear() 2011-10-18 15:43:22 -06:00
Thomas Hellstrom
6235846cb7 svga: Plug a fence leak 
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
 2011-10-18 10:37:12 +02:00
Stéphane Marchesin
0b3842edb1 i915g: Use the right shader limits. 2011-10-17 21:43:46 -07:00
Stéphane Marchesin
3637b5f0dd i915g: Add TODO. 2011-10-17 21:43:46 -07:00
Mathias Fröhlich
e556983fc8 r600g: Use the bitfield define matching the register it is used for. 
Fix a typo that should result in the same code.
 2011-10-18 06:35:21 +02:00
Tom Stellard
53d32600cc r300/compiler: Try to eliminate REPL_ALPHA instructions 
Scalar instruction that need to write to the xyz components of a
register must reserve the RGB instruction slot for a REPL_ALPHA
instruction.  With this commit, the scheduler will attempt to free
the RGB slot by moving the write to the w component of a register.
 2011-10-16 19:54:48 -07:00
Tom Stellard
8327fd18c9 r300/compiler: More agressive RGB to Alpha conversions 2011-10-16 19:54:48 -07:00
Tom Stellard
653c7af3d6 r300/compiler: Only convert RGB->Alpha when optimizations are enabled 2011-10-16 19:54:48 -07:00
José Fonseca
e9c1d87ce7 llvmpipe: Use lp_build_ifloor_fract for exp2 calculation. 
Instead of separate ifloor / fract calls.

No change for SSE4.1 code, but less FP<->SI conversions on non SSE4.1
systems.
 2011-10-16 14:18:41 +01:00
Marek Olšák
1350882e49 Revert "r300g: fix rendering with a non-zero index bias in draw_elements_immediate" 
This reverts commit 5506f6ef96.

It breaks more things than it fixes.
 2011-10-16 03:19:11 +02:00
Christoph Bumiller
9934bfe28d nv50,nvc0: extend formats table for integer formats 2011-10-15 14:12:31 +02:00
Tom Stellard
0dc97e7fd4 r300/compiler: Enable reg rename pass on r500 and run it before optimizations 
The scheduler and the register allocator are now smart enough to handle
it.
 2011-10-14 18:30:14 -07:00
Tom Stellard
163629fd05 r300/compiler: Implement the texture semaphore 
The texture semaphore allows for prefetching of texture data.  On my
RV515, this increases the FPS of Lightsmark by 33% (This is with the
reg_rename pass enabled, which is enabled in the next commit).

There is a new env variable now called RADEON_TEX_GROUP, which allows
you to specify the maximum number of texture lookups to do at once.
The default is 8, but different values could produce better results
for various application / card combinations.
 2011-10-14 18:30:14 -07:00
Tom Stellard
51fe9994bd r300/compiler: Don't pair output writes with GPR writes in the scheduler 2011-10-14 18:30:14 -07:00
Tom Stellard
6fafb6beb7 r300/compiler: Prevent regalloc from creating non-native swizzles 2011-10-14 18:30:14 -07:00
Tom Stellard
47c7512846 r300/compiler: Allow merged instructions to be scheduled on demand 
We no longer emit full instructions immediately after they have been
merged.  Instead merged instructions are added to the ready list and
the scheduler can commit them whenever it wants.
 2011-10-14 18:30:14 -07:00
Marek Olšák
ae272a92a1 r300g: set max vertex samplers to 0 on swtcl chipsets 
This should fix a bug added by f5bfe54a.

Might also fix:
https://bugs.freedesktop.org/show_bug.cgi?id=41715
 2011-10-14 15:06:01 +02:00
Dave Airlie
ae1153c4ac softpipe: fix regression with tex tile cache since integer support. 
Don't use the uint/int paths for ZS formats for tex tile cache.

fixes: https://bugs.freedesktop.org/show_bug.cgi?id=41695

Signed-off-by: Dave Airlie <airlied@redhat.com>
 2011-10-12 08:25:28 +01:00