Commit graph

117072 commits

Author SHA1 Message Date
Marek Olšák
56e3c70b56 radeonsi/nir: accurately set output_usagemask (v2)
v2: fix doubles
2019-07-30 22:06:23 -04:00
Marek Olšák
37527f8a11 radeonsi/nir: accurately set reads_*_outputs for TCS 2019-07-30 22:06:23 -04:00
Marek Olšák
6697e42c3c radeonsi/nir: clean up gather_intrinsic_load_deref_input_info 2019-07-30 22:06:23 -04:00
Marek Olšák
5f16fdefdf radeonsi/nir: add an option to convert TGSI to NIR
Use at your own risk.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-30 22:06:23 -04:00
Marek Olšák
eb43559bb8 radeonsi/nir: clean up some nir_scan_shader code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-30 22:06:23 -04:00
Marek Olšák
34dc6ed2a5 radeonsi/gfx10: disable DCC image stores
Uncompressed image stores are usually faster.

Also, the driver didn't set WRITE_COMPRESS_ENABLE, so I don't know
what the hw did for image stores.
2019-07-30 22:06:23 -04:00
Marek Olšák
17021efc74 radeonsi: adjust RB+ blend optimization settings
based on PAL
2019-07-30 22:06:23 -04:00
Marek Olšák
27ac9a3326 ac/surface: allow linear swizzle mode automatic selection on gfx9 & 10
let addrlib make the decision to get the same result as PAL.
2019-07-30 22:06:23 -04:00
Pierre-Eric Pelloux-Prayer
a0ac0e2653 mesa: add EXT_dsa indexed generic queries
Only GetPointerIndexedvEXT needs an implementation, the other functions are
aliases of existing functions.
2019-07-30 22:04:26 -04:00
Pierre-Eric Pelloux-Prayer
ef84d93f3d mesa: add EXT_dsa indexed texture commands functions
Added functions:
  - EnableClientStateIndexedEXT
  - DisableClientStateIndexedEXT
  - EnableClientStateiEXT
  - DisableClientStateiEXT

Implemented using the idiom provided by the spec:

        if (array == TEXTURE_COORD_ARRAY) {
          int savedClientActiveTexture;

          GetIntegerv(CLIENT_ACTIVE_TEXTURE, &savedClientActiveTexture);
          ClientActiveTexture(TEXTURE0+index);
          XXX(array);
          ClientActiveTexture(savedActiveTexture);
        } else {
          // Invalid enum
        }
2019-07-30 22:04:26 -04:00
Pierre-Eric Pelloux-Prayer
7534c536ca mesa: add EXT_dsa (Named)Framebuffer functions
These functions dont support display list as specified:

    Should the selector-free versions of various OpenGL 3.0 and
    EXT_framebuffer_object framebuffer object commands not be allowed
    in display lists [...]?

    RESOLVED:  Yes
2019-07-30 22:04:26 -04:00
Pierre-Eric Pelloux-Prayer
e26c6764f2 mesa: add EXT_dsa NamedBuffer functions 2019-07-30 22:04:26 -04:00
Jason Ekstrand
9265e9d11a i965/curbe: Look at SYSTEM_VALUE_FRAG_COORD instead of VARYING_SLOT_POS
When transitioning gl_FragCoord over to a system value, we missed one
instance of VARYING_SLOT_POS in i965.  As of this commit, i965 has no
references to VARYING_SLOT_POS.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111263
Fixes: 4bb6e6817e "intel: Use a system value for gl_FragCoord"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 19:21:09 -05:00
Jason Ekstrand
8fd2f2c276 intel/fs: Implement quad_swap_horizontal with a swizzle on gen7
This fixes dEQP-VK.subgroups.quad.compute.subgroupquadswaphorizontal_*
on all gen7 platforms.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-30 22:38:19 +00:00
Jason Ekstrand
499d760c6e intel/fs: Use ALIGN16 instructions for all derivatives on gen <= 7
The issue here was discovered by a set of Vulkan CTS tests:

    dEQP-VK.glsl.derivate.*.dynamic_*

These tests use ballot ops to construct a branch condition that takes
the same path for each 2x2 quad but may not be uniform across the whole
subgroup.  They then tests that derivatives work and give the correct
value even when executed inside such a branch.  Because the derivative
isn't executed in uniform control-flow and the values coming into the
derivative aren't smooth (or worse, linear), they nicely catch bugs that
aren't uncovered by simpler derivative tests.

Unfortunately, these tests require Vulkan and the equivalent GL test
would require the GL_ARB_shader_ballot extension which requires int64.
Because the requirements for these tests are so high, it's not easy to
test on older hardware and the bug is only proven to exist on gen7;
gen4-6 are a conjecture.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-30 22:38:19 +00:00
Eric Engestrom
bf8b5de6b9 scons+meson: suppress spammy build warning on MacOS
Originally introduced in c7f3657450 ("darwin: Suppress type
conversion warnings for GLhandleARB") to fix Bugzilla #66346 [1], this
workaround was never ported to Scons or Meson.

[1] https://bugs.freedesktop.org/66346

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-07-30 23:21:42 +01:00
Matt Turner
46a3ea06be i965/fs: Print the scheduler mode.
Line wrap some awfully long lines while we are here.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-07-30 14:35:43 -07:00
Matt Turner
dabb5d4bee i965/fs: Add a shader_stats struct.
It'll grow further, and we'd like to avoid adding an additional
parameter to fs_generator() for each new piece of data.

v2 (idr): Rebase on 17 months.  Track a visitor instead of a cfg.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-30 14:35:43 -07:00
Connor Abbott
11a49f289d lima/gp: Support exp2 and log2
log2 is tricky because there cannot be a move between complex1 and
postlog2. We can't guarantee that scheduling complex1 will succeed when
we schedule postlog2, so we try to schedule complex1 and if it fails we
back out by rewriting the postlog2 as a move and introducing a new
postlog2 so that we can try again later.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Qiang Yu <yuq825@gmail.com>
2019-07-30 23:01:15 +02:00
Connor Abbott
c2f48d8f32 lima/gpir: Always schedule complex2 and *_impl right after complex1
See https://gitlab.freedesktop.org/lima/mesa/issues/94 for the gory
details of why this is needed. For *_impl this is easy, since it never
increases register pressure and it goes in the complex slot hence it
never counts against max nodes. It's a bit more challenging for
complex2, since it does count against max nodes, so we need to change
the reservation logic to reserve an extra slot for complex2 when
scheduling complex1. This second part isn't strictly necessary yet, but
it will be for exp2.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Qiang Yu <yuq825@gmail.com>
2019-07-30 23:00:41 +02:00
Bas Nieuwenhuizen
2b53c49d2f radv: Fix descriptor set allocation failure.
Set all the handles to VK_NULL_HANDLE:

"If the creation of any of those descriptor sets fails, then the implementation
must destroy all successfully created descriptor set objects from this command,
set all entries of the pDescriptorSets array to VK_NULL_HANDLE and return the
error."

(Vulkan 1.1.117 Spec, section 13.2)

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-30 22:33:24 +02:00
Andres Rodriguez
2b71b4e793 radv: fix queries with WAIT_BIT returning VK_NOT_READY
When vkGetQueryPoolResults() is called with VK_QUERY_RESULT_WAIT_BIT
set, the driver is supposed to wait for the query to become available
before returning.

Currently, radv returns once the query is indeed ready, but it returns
VK_NOT_READY. It also fails to populate the results.

The problem is a missing volatile in the secondary check for query
availability. This patch removes the secondary check altogether since it
is redundant with the preceding loop.

This bug was found with an unreleased version of SteamVR.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-27 10:19:19 -04:00
Matt Turner
c9b86cf526 meson: Test for program_invocation_name
program_invocation_name and program_invocation_short_name are both GNU
extensions. I don't believe one can exist without the other, so only
check for program_invocation_name.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-30 11:49:09 -07:00
Matt Turner
597bddad47 scons: Test for random_r()
Suggested-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-30 11:49:09 -07:00
Matt Turner
c96407f37e meson: Test for random_r()
It's better to test for needed functions instead of using external
knowledge about presence in this or that C library.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-30 11:49:09 -07:00
Matt Turner
9cc4311d86 st/nine: Drop preprocessor guards for glibc-2.12
Same rationale as the previous patch, but additionally these checks just
seem entirely unnecessary. pthread_self() has been used in Mesa since at
least 1999.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-30 11:49:09 -07:00
Matt Turner
9c411e020d util: Drop preprocessor guards for glibc-2.12
glibc-2.12 was released in 2010. No one is building new Mesa against 9
year old glibc, and removing these checks allows the code to work on
other C libraries like musl.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2019-07-30 11:49:09 -07:00
Alyssa Rosenzweig
a3c59f9f00 pan/midgard: Nothing to see here, move along folks
Fixes: dee1e18fe4 ("pan/midgard: Cleanup ops table")

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:49:13 -07:00
Lionel Landwerlin
7deb5ec0e8 spirv: don't discard access set by vtn_pointer_dereference
We can have a access flag already set here so just augment the
existing ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0fb61dfdeb ("spirv: propagate access qualifiers through ssa & pointer")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-30 17:43:59 +00:00
Sagar Ghuge
587a497529 iris: Enable EXT_texture_shadow_lod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 10:42:20 -07:00
Sagar Ghuge
adb9e18348 gallium: Add PIPE_CAP_TEXTURE_SHADOW_LOD
v2: Line wrap to 80 char (Marek Olsak)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 10:42:20 -07:00
Sagar Ghuge
6e04bd5f13 i965: Enable EXT_texture_shadow_lod
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 10:42:20 -07:00
Paulo Zanoni
25b03526c4 glsl: Add builtin functions for EXT_texture_shadow_lod
With the help of Sagar, Ian and Ivan.

v2: Fix dependencies (Ian Romanick)

v3: 1) fix function name (Marek Olsak)
    2) Add check for extension enable (Marek Olsak)

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 10:42:20 -07:00
Paulo Zanoni
154c789ad5 glsl: Allow _textureCubeArrayShadow function to accept ir_texture_opcode
This will be used to support one of the function from
Ext_texture_shadow_lod specification.

With the help of Sagar, Ian and Ivan.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 10:42:20 -07:00
Paulo Zanoni
d80a74fb99 mesa: extension boilerplate for EXT_texture_shadow_lod
With the help of Sagar, Ian and Ivan.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-30 10:42:20 -07:00
Alyssa Rosenzweig
dee1e18fe4 pan/midgard: Cleanup ops table
Hopefully this should make a few ops make more sense. No functional
changes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:35:22 -07:00
Alyssa Rosenzweig
834aeb1e52 pan/midgard: Extend copy-propagation to swizzles
We can compose them when we rewrite, which is.. more code.. but helps.

total instructions in shared programs: 3611 -> 3513 (-2.71%)
instructions in affected programs: 672 -> 574 (-14.58%)
helped: 11
HURT: 2
helped stats (abs) min: 2 max: 14 x̄: 9.09 x̃: 10
helped stats (rel) min: 5.71% max: 24.56% x̄: 17.99% x̃: 18.87%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.19% max: 2.08% x̄: 1.64% x̃: 1.64%
95% mean confidence interval for instructions value: -10.45 -4.62
95% mean confidence interval for instructions %-change: -20.07% -9.87%
Instructions are helped.

total bundles in shared programs: 2117 -> 2067 (-2.36%)
bundles in affected programs: 356 -> 306 (-14.04%)
helped: 11
HURT: 0
helped stats (abs) min: 1 max: 7 x̄: 4.55 x̃: 5
helped stats (rel) min: 4.55% max: 15.22% x̄: 13.63% x̃: 14.71%
95% mean confidence interval for bundles value: -5.64 -3.45
95% mean confidence interval for bundles %-change: -15.71% -11.55%
Bundles are helped.

total quadwords in shared programs: 3567 -> 3468 (-2.78%)
quadwords in affected programs: 695 -> 596 (-14.24%)
helped: 11
HURT: 1
helped stats (abs) min: 2 max: 14 x̄: 9.09 x̃: 10
helped stats (rel) min: 5.56% max: 21.88% x̄: 14.97% x̃: 15.15%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 2.38% max: 2.38% x̄: 2.38% x̃: 2.38%
95% mean confidence interval for quadwords value: -10.96 -5.54
95% mean confidence interval for quadwords %-change: -17.42% -9.63%
Quadwords are helped.

total registers in shared programs: 391 -> 383 (-2.05%)
registers in affected programs: 46 -> 38 (-17.39%)
helped: 9
HURT: 1
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 10.00% max: 10.00% x̄: 10.00% x̃: 10.00%
95% mean confidence interval for registers value: -1.25 -0.35
95% mean confidence interval for registers %-change: -29.42% -13.58%
Registers are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:35:10 -07:00
Alyssa Rosenzweig
c45487b770 pan/midgard: Extract simple source mod check
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:35:09 -07:00
Alyssa Rosenzweig
2d2abb08d0 pan/midgard: Lower texr/texw mixed registers
Conceptually, r28-r29 (as used for reading) and r28-r29 (as used for
writing) aren't registers at all, merely push/pull arrangements. So you
can't feed a texture result back into itself without explicitly moving
in the middle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:20 -07:00
Alyssa Rosenzweig
2b248af43e pan/midgard: Always set .cont for derivatives in loops
We need to keep the helper invocations alive.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
8f887329c0 pan/midgard: Implement derivatives
Implement the fdd* and fdd* opcodes in the Midgard compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
982134d22e pan/midgard: Compose original texture swizzle in RA
Used for lowering derivatives.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
79875a9a64 pan/midgard: Add new swizzles
Used for derivatives.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
81e7782e30 pan/midgard: Add OP_IS_DERIVATIVE helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
ae6aea0d98 pan/midgard: Add make_compiler_temp_reg helper
Corrollary to make_compiler_temp (for SSA).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
30b15a830a pan/midgard: Move nir_*_src_index to compiler.h
These helpers are useful for code emission everywhere. Share the love!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
c9498b3c5e pan/midgard: Disassemble unknown texture ops as hex
I'm not sure why I ever thought decimal was a good idea.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Alyssa Rosenzweig
0714481894 pan/midgard: Add support for disassembling derivatives
They're just texture ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-30 10:01:19 -07:00
Connor Abbott
a094928abc nir/find_array_copies: Use correct parent array length
instr->type is the type of the array element, not the type of the array
being dereferenced. Rather than fishing out the parent type, just use
parent->num_children which should be the length plus 1. While we're here
add another assert for the issue fixed by the previous commit.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111251
Fixes: 156306e5e6 ("nir/find_array_copies: Handle wildcards and overlapping copies")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-07-30 17:14:33 +02:00
Connor Abbott
7788992bc6 nir: Fix comparison for nir_deref_instr_is_known_out_of_bounds()
There was an off-by-one error.

Fixes: 156306e5e6 ("nir/find_array_copies: Handle wildcards and overlapping copies")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-07-30 17:14:28 +02:00