Commit graph

117072 commits

Author SHA1 Message Date
Jason Ekstrand
d28bc35ece intel/fs: Add an assert to optimize_frontfacing_ternary
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:25 -06:00
Jason Ekstrand
bcc6aab065 anv: Use nir_src_is_const and friends in lowering code
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:25 -06:00
Jason Ekstrand
52145070c0 intel/analyze_ubo_ranges: Use nir_src_is_const and friends
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:25 -06:00
Jason Ekstrand
1413512b4c intel/vec4: Use the new nir_src_is_const and friends
As of this commit, all uses of const sources either go through a
nir_src_as_<type> helper which handles bit sizes correctly or else are
accompanied by a nir_src_bit_size() == 32 assertion to assert that we
have the size we think we have.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:25 -06:00
Jason Ekstrand
61e15348c4 nir: Add a read_mask helper for ALU instructions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:22 -06:00
Jason Ekstrand
344cfe6980 intel/fs: Use the new nir_src_is_const and friends
As of this commit, all uses of const sources either go through a
nir_src_as_<type> helper which handles bit sizes correctly or else are
accompanied by a nir_src_bit_size() == 32 assertion to assert that we
have the size we think we have.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:20 -06:00
Jason Ekstrand
6b2918709a intel/fs,vec4: Clean up a repeated pattern with SSBOs
Everywhere we handle SSBO intrinsics, we have exactly the same pattern
for computing the index so we may as well make a helper for it.  We also
add a get_nir_src_imm to vec4 and use it for SSBO offsets.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-08 10:09:06 -06:00
Samuel Pitoiset
c472ad82e4 radv: fix GPU hangs when loading depth/stencil clear values on SI/CIK
HTILE is supported on these chips, not sure how I missed that.
This restores using PFP_SYNC_ME when LOAD_CONTEXT_REG is not used.

Fixes: f425d9ee74 ("radv: use LOAD_CONTEXT_REG when loading fast clear values")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-11-08 11:20:03 +01:00
Samuel Pitoiset
f425d9ee74 radv: use LOAD_CONTEXT_REG when loading fast clear values
This avoids syncing the Micro Engine. This is only supported
for VI+ currently. There is probably a way for using
LOAD_CONTEXT_REG on previous chips but that could be done later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-08 10:41:45 +01:00
Samuel Pitoiset
0dcd99c687 radv: only expose VK_SUBGROUP_FEATURE_ARITHMETIC_BIT for VI+
Inclusive and exclusives scan are missing because older chips
don't have llvm.amdgcn.update.dpp.

This fixes crashes with dEQP-VK.subgroups.arithmetic.*.

CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-08 10:41:41 +01:00
Adam Jackson
16f1023037 glx: Demand success from CreateContext requests (v2)
GLXCreate{,New}Context, like most X resource creation requests, does not
emit a reply and therefore is emitted into the X stream asynchronously.
However, unlike most resource creation requests, the GLXContext we
return is a handle to library state instead of an XID. So if context
creation fails for any reason - say, the server doesn't support indirect
contexts - then we will fail in strange places for strange reasons.

We could make every GLX entrypoint robust against half-created contexts,
or we could just verify that context creation worked. Reuse the
__glXIsDirect code to do this, as a cheap way of verifying that the
XID is real.

glXCreateContextAttribsARB solves this by using the _checked version of
the xcb command, so effectively this change makes the classic context
creation paths as robust as CreateContextAttribs.

v2: Better use of Bool, check that error != NULL first (Olivier Fourdan)

Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-11-07 12:38:05 -05:00
Karol Herbst
f7fae7f64e gm107/ir: fix compile time warning in getTEXSMask
In function 'uint8_t nv50_ir::getTEXSMask(uint8_t)':
warning: control reaches end of non-void function [-Wreturn-type]

Reported-by: Moiman@freenode
Fixes: f821e80213
       "gm107/ir: use scalar tex instructions where possible"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-11-07 17:48:58 +01:00
Michel Dänzer
32b0eb51a3 winsys/amdgpu: Stop using amdgpu_bo_handle_type_kms_noimport
It only behaves any different from amdgpu_bo_handle_type_kms with
libdrm 2.4.93, and it breaks if an older version is picked up.

Bugzilla: https://bugs.freedesktop.org/108096
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-11-07 17:37:47 +01:00
Lionel Landwerlin
792dde66f2 intel/dump_gpu: add platform option
Got tired of remembering the PCI ids.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-07 11:27:41 +00:00
Lionel Landwerlin
e262cc0353 intel/dump_gpu: move output option together
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-07 11:27:38 +00:00
Samuel Pitoiset
0a0aa2ba6c radv: disable conditional rendering for vkCmdCopyQueryPoolResults()
VK_EXT_conditional_rendering says that copy commands should not be
affected by conditional rendering.

Cc: 18.2 18.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-07 11:31:36 +01:00
Samuel Pitoiset
1e7c3379e1 radv: allocate enough space in CS when copying query results with compute
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-07 11:31:34 +01:00
Timothy Arceri
9aa3c1915e ac/nir_to_llvm: fix b2f for f64
Fixes: d7e0d47b9d ("nir: Add a bunch of b2[if] optimizations")

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-07 16:35:07 +11:00
Karol Herbst
f821e80213 gm107/ir: use scalar tex instructions where possible
TEXS, TLD4 and TLD4S are variants of tex instructions which are more
scalar, which gives RA more freedom and is less likely to insert silly
MOVs to satisfy quad registers.

shader-db changes:
total instructions in shared programs : 7687265 -> 7614782 (-0.94%)
total gprs used in shared programs    : 803620 -> 798045 (-0.69%)
total shared used in shared programs  : 639636 -> 639636 (0.00%)
total local used in shared programs   : 24648 -> 24648 (0.00%)
total bytes used in shared programs   : 82103400 -> 81330696 (-0.94%)

                local     shared        gpr       inst      bytes
    helped           0           0        3648       10647       10647
      hurt           0           0         464         205         205

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-11-06 19:57:05 +01:00
Karol Herbst
edd6c41751 nv50/ir: add scalar field to TexInstructions
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-11-06 19:57:05 +01:00
Karol Herbst
8d825f78fc nv50/ra: add condenseDef overloads for partial condenses
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-11-06 19:57:05 +01:00
Karol Herbst
a4550de434 nv50/ir: print color masks of tex instructions
v2: print the mask for TXG as well
    make the mask to be printed more mask like

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-11-06 19:57:05 +01:00
Jason Ekstrand
610061838a vulkan: Update the XML and headers to 1.1.91
The biggest change here is the rename of VK_NVX_ray_tracing to
VK_NV_ray_tracing and the total removal of VK_KHR_mir_surface.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-06 12:21:19 -06:00
Gert Wollny
c171d76b94 r600: Add support for EXT_texture_sRGB_R8
Enables on R600 and makes pass:
  dEQP-GLES31.functional.srgb_texture_decode.skip_decode.sr8.*
  dEQP-GLES31.functional.texture.filtering.cube_array.formats.sr8*

v2: remove chunk for dri/radeon (Emil)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-11-06 18:49:02 +01:00
Lionel Landwerlin
421fa01d64 anv/android: mark gralloc allocated BOs as external
Allocating through Gralloc implies buffers are going to be used
outside the driver. We have special MOCS settings for external BOs and
we probably want to use them here too.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a1220e7311 ("anv/android: Set the BO flags in bo_cache_import (v2)")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-06 15:28:07 +00:00
Lionel Landwerlin
b43f955037 anv: stub internal android code
This reduces the amount of #ifdef ANDROID we'll have to have inside
the driver. Potentially offering better coverage of the android
extensions.

v2: Move anv_android.h include before anv_entrypoints.h (Tapani)
    Fix autotools android build (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-06 15:28:07 +00:00
Kristian H. Kristensen
f6131d4ec7 freedreno/a6xx: Clear z32 and separate stencil with blitter
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2018-11-06 08:56:38 -05:00
Rob Clark
3bbad81c80 freedreno/a6xx: fix VSC bug with larger # of tiles
At higher resolutions with the addition of MSAA, the number of tiles
can increase to the point where we use more than one VSC pipe per
tile.  Which would cause us to calculate an out-of-bounds offset for
VSC_SIZE_ADDRESS.  So don't try to be clever, just always put it at
a fixed offset assuming the max 32 VSC pipes in use.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-06 08:56:21 -05:00
Rob Clark
2d9c3a5db2 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-06 08:43:27 -05:00
Olivier Fourdan
55af17ffed wayland/egl: Resize EGL surface on update buffer for swrast
After commit a9fb331ea ("wayland/egl: update surface size on window
resize"), the surface size is updated as soon as the resize is done, and
`update_buffers()` would resize only if the surface size differs from
the attached size.

However, in the case of swrast, there is no resize callback and the
attached size is updated in `dri2_wl_swrast_commit_backbuffer()` prior
to the `swrast_update_buffers()` so the attached size is always up to
date when it reaches `swrast_update_buffers()` and the surface is never
resized.

This can be observed with "totem" using the GDK backend on Wayland (the
default) when running on software rendering:

  $ LIBGL_ALWAYS_SOFTWARE=true CLUTTER_BACKEND=gdk totem

Resizing the window would leave the EGL surface size unchanged.

To avoid the issue, partially revert the part of commit a9fb331ea for
`swrast_update_buffers()` and resize on the win size and not the
attached size.

Fixes: a9fb331ea - wayland/egl: update surface size on window resize
Signed-off-by: Olivier Fourdan <ofourdan@redhat.com>
CC: Daniel Stone <daniel@fooishbar.org>
CC: Juan A. Suarez Romero <jasuarez@igalia.com>
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
2018-11-06 13:59:38 +01:00
Lionel Landwerlin
b47a69ed4c intel/decoders: fix instruction base address parsing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 00103db04a ("intel: Fix decoding for partial STATE_BASE_ADDRESS updates.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-05 13:22:35 -08:00
Emil Velikov
b3ade65387 egl/glvnd: correctly report errors when vendor cannot be found
If the user provides an invalid display or device the ToVendor lookup
will fail.

In this case, the local [Mesa vendor] error code will be set. Thus on
sequential eglGetError(), the error will be EGL_SUCCESS.

To be more specific, GLVND remembers the last vendor and calls back
into it's eglGetError, although there's no guarantee to ever have had
one.

v2:
 - Add _eglError call, so the debug callback is executed (Kyle)
 - Drop XXX comment.

Piglit: tests/egl/spec/egl_ext_device_query
Fixes: ce562f9e3f ("EGL: Implement the libglvnd interface for EGL (v3)")
Cc: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Kyle Brenneman <kbrenneman@nvidia.com>
2018-11-05 20:53:05 +00:00
Emil Velikov
2a8fefdeb0 egl: add EGL_EXT_device_base entrypoints
eglQueryDevicesEXT (unlike the other three functions) does not depend
on the display. It is implemented in GLVND, which calls into each
driver collecting the list of devices and presenting it to the user.

For the other entrypoints, GLVND acts as pass through stub calling into
the vendor library. The vendor implementation calls back into GLVND to
get the vendor dispatch. Then the driver proceeds to call itself via
the said dispatch.

This design makes is possible to keep using "old" GLVND with newer
vendor drivers. Since effectively all the extension code is within the
latter itself.

Without said entrypoints, any user will outright crash - as reported in
the bug report.

Note: there's a follow-up fix needed to our GLVND code, to make piglit
happy.

v2: add some beefy documentation in the commit message.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108635
Fixes: 7552fcb7b9 ("egl: add base EGL_EXT_device_base implementation")
Reported-by: kyle.devir@mykolab.com
Cc: kyle.devir@mykolab.com
Acked-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-05 20:53:05 +00:00
Emil Velikov
7e169cf2a0 docs: mention EXT_shader_implicit_conversions
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-05 20:53:05 +00:00
Marek Olšák
04298a2f24 st/va: fix incorrect use of resource_destroy
Fixes: 4373dd3215 ("st/va: Support YUV formats in vaCreateSurfaces")
Cc: Drew Davenport <ddavenport@chromium.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-11-05 15:47:50 -05:00
Sergii Romantsov
5aeee1ab15 i965/batch/debug: Allow log be dumped before assert
Message that may show the culprit of assert now will
be dumped before that for debug purposes.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel G Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-11-05 09:24:55 -08:00
Lionel Landwerlin
4fd0ff75f3 intel/sanitize_gpu: add debug message on mmap fail
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-05 15:45:08 +00:00
Lionel Landwerlin
e400ac52e4 intel/sanitize_gpu: deal with non page multiple buffer sizes
We can only map at page aligned offsets. We got that wrong with buffer
size where (size % 4096) != 0 (anv has a WA buffer of 1024).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-05 15:45:07 +00:00
Lionel Landwerlin
c5fca35af1 intel/sanitize_gpu: add help/gdb options to wrapper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-05 15:45:07 +00:00
Lionel Landwerlin
9ab5089150 intel/dump_gpu: add missing gdb option
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-05 15:43:34 +00:00
Eric Engestrom
d515ded4d9 wsi/wayland: only finish() a successfully init()ed display
Fixes: 4369102498 "vulkan/wsi/wayland: Stop caching Wayland displays"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05 15:29:21 +00:00
Eric Engestrom
dcee22afed wsi/wayland: use proper VkResult type
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-05 14:55:05 +00:00
Sergii Romantsov
ce837a5372 autotools: library-dependency when no sse and 32-bit
Building of 32bit Mesa may fail if __SSE__ is not specified.
Added missed dependency from libm.

v2: avoided dependecy on any flag, just link

v3: meson doesn't fail, but have added dependency on libm

CC: Dylan Baker <dylan@pnwbakers.com>
CC: Lionel G Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108560
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-11-05 13:21:49 +01:00
Samuel Pitoiset
f7fd0d86a9 radv: more use of radv_cp_wait_mem()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-05 09:48:50 +01:00
Samuel Pitoiset
c571ca7a08 radv: replace si_emit_wait_fence() with radv_cp_wait_mem()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-05 09:48:50 +01:00
Samuel Pitoiset
b1b2dd06a7 radv: add missing TFB queries support to CmdCopyQueryPoolsResults()
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
Fixes: b4eb029062 ("radv: implement VK_EXT_transform_feedback")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-05 09:48:43 +01:00
Samuel Pitoiset
dc3419195c radv: remove useless sync after copying query results with compute
The spec says:
   "vkCmdCopyQueryPoolResults is considered to be a transfer
    operation, and its writes to buffer memory must be synchronized
    using VK_PIPELINE_STAGE_TRANSFER_BIT and VK_ACCESS_TRANSFER_WRITE_BIT
    before using the results."

VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle,
while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector
caches and L2. So, it's useless to set those flags internally.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-05 09:47:55 +01:00
Vinson Lee
64a9ed8848 r600/sb: Fix constant logical operand in assert.
Fixes: da977ad907 ("r600/sb: start adding GDS support")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2018-11-04 21:09:55 -08:00
Kenneth Graunke
5d517a599b st/mesa: Don't record garbage streamout information in the non-SSO case.
In the non-SSO case, where multiple shader stages are linked together,
we were recording garbage pipe_stream_output_info structures for all
but the last enabled geometry-processing stage.

Specifically, we were using the gl_transform_feedback_info from
shader_program->last_vert_prog (the stage whose outputs will be
recorded)...but were pairing it with the output varying mappings
from the current shader stage.  For example, a program with a VS and
GS, the VS's pipe_shader_state would have a pipe_stream_output_info
based on the GS transform feedback info, but the VS output mapping.

This generally worked out okay because only the pipe_stream_output_info
for the last stage really matters - the others can be ignored.  However,
we'd like to avoid confusing the pipe driver.  In particular, my new
driver translates the stream out information to hardware packets at
bind_{vs,tes,gs}_state() time...and was hitting asserts about garbage
varyings that didn't exist.

This patch changes st/mesa to record a blank pipe_stream_output_info
with num_outputs = 0 for all stages prior to last_vert_prog.  The last
one is captured as normal.

(In the fully-SSO case, nothing should change - each program contains
a single shader stage, so last_vert_prog *is* the current shader.)

Tested with llvmpipe (piglit's gpu profile), and freedreno (a3xx,
gpu profile with -t transform.feedback).  Fixes several hundred CTS
tests on my new driver.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-11-03 23:34:36 -07:00
Kenneth Graunke
b6410a2d22 st/nir: Drop unused parameter from st_nir_assign_uniform_locations().
ARB programs won't have one of these, and we don't use it anyway.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-11-03 23:34:36 -07:00