Commit graph

117072 commits

Author SHA1 Message Date
Jonathan Marek
467f9982df turnip: fix segmentation fault with compute pipeline
Not supported, so always set pointer to NULL

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-15 07:56:19 -04:00
Jonathan Marek
eef195c9cc turnip: fix segmentation fault in events
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-15 07:56:19 -04:00
Jonathan Marek
03772df450 turnip: fix 32 vertex attributes case
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-15 07:56:19 -04:00
Jonathan Marek
8580726f90 turnip: fix triangle strip
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-15 07:56:19 -04:00
Jonathan Marek
b7093882eb freedreno/regs: update a6xx 2d blit bits
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-15 07:56:18 -04:00
Samuel Pitoiset
50c8c4144b radv: rename VK_KHR_shader_float16_int8 structs/constants
Trivial change.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-15 12:13:53 +02:00
Iago Toral
e353656f3d v3d: drop unused shader_rec_count member from context
Looks like this was copied from the vc4 driver where it is actually
included in the submit CL ioctl.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-10-15 06:56:45 +00:00
Jonathan Marek
278c9b5cc7 freedreno/ir3: implement fquantize2f16
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>
2019-10-14 17:48:22 -04:00
Jonathan Marek
92d756f22d freedreno/ir3: implement texop_texture_samples
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>
2019-10-14 17:48:22 -04:00
Jonathan Marek
3cfd5ffb8c freedreno/ir3: fix GETLOD for negative LODs
Note: for output type U32, negative LOD is not sign extended from 16 bits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>
2019-10-14 17:48:22 -04:00
Jonathan Marek
cfc6a3e394 freedreno/ir3: implement fdd{x,y}_coarse opcodes
Same as regular fddx/fddy.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>
2019-10-14 17:48:22 -04:00
Jonathan Marek
b094b384e2 freedreno/ir3: increase size of inputs/outputs arrays
Makes it possible to support 32 varyings.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>
2019-10-14 17:48:22 -04:00
Jonathan Marek
08003c37b9 freedreno/ir3: remove input ncomp field
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robclark@gmail.com>
2019-10-14 17:48:22 -04:00
Lucas Stach
ce23bc9283 etnaviv: fix vertex buffer state emission for single stream GPUs
GPUs with a single supported vertex stream must use the single state
address to program the stream.

Fixes: 3d09bb390a (etnaviv: GC7000: State changes for HALTI3..5)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
2019-10-14 19:18:37 +00:00
Dave Airlie
c2efc7c637 gallivm/draw/swr: make the gs_iface not depend on tgsi.
This gs_iface doesn't seem to require a dependence on the tgsi
context, except for the swr end prim code.

This refactors the API to include all the info that the swr
code needs in the interface rather than having to dig it out of
the struct inheritance.

This is a precursor to adding NIR support to llvmpipe.

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
2019-10-15 04:43:30 +10:00
Kenneth Graunke
ac7af7c500 iris: Implement the Gen < 9 tessellation quads workaround
Fixes several CTS tests:
- KHR-GL46.tessellation_shader.vertex.vertex_spacing
- KHR-GL46.tessellation_shader.tessellation_shader_point_mode.points_verification

Fixes: 823609b1a3 ("iris/WIP: add broadwell support")
2019-10-14 09:48:36 -07:00
Caio Marcelo de Oliveira Filho
58286c7969 anv: Advertise VK_KHR_spirv_1_4
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-14 08:25:42 -07:00
Caio Marcelo de Oliveira Filho
90a7893ca8 vulkan: Update the XML and headers to 1.1.125
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-14 08:23:27 -07:00
Mauro Rossi
072c94f724 android: amd/common: export amd/llvm headers
Fixes the following building error:

external/mesa/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c:42:10:
fatal error: 'ac_llvm_util.h' file not found
         ^~~~~~~~~~~~~~~~
1 error generated.

Fixes: 3a08110 ("amd: Move all amd/common code that depends on LLVM to amd/llvm.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-14 10:46:45 +02:00
James Xiong
4f963b03a1 gallium: rename PIPE_CAP_MAX_FRAMES_IN_FLIGHT to PIPE_CAP_THROTTLE
v2: [ Michel Dänzer ]
* Update src/gallium/docs/source/screen.rst accordingly

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com> # v1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> # v1
2019-10-14 10:05:46 +02:00
James Xiong
a65e29ccb2 gallium: simplify throttle implementation
All gallium drivers currently set MAX_FRAME_IN_FLIGHT to either 1
or 0, which means that the drivers either throttle on the previous
render or don't throttle, the current implementation is more
complicated than necessary and can be simplified.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-10-14 10:05:40 +02:00
Samuel Pitoiset
ea92273cea radv: fix DCC fast clear code for intensity formats
This fixes a rendering issue with DiRT 4 on GFX10. Only GFX10 was
affected because intensity formats are different.

Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1923
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-14 08:36:14 +02:00
Eric Engestrom
ebe176eeff gbm: use size_t for array indexes
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-10-13 18:10:47 +01:00
Eric Engestrom
ad7e410893 gbm: replace NULL sentinel with explicit ARRAY_SIZE()
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-10-13 18:10:47 +01:00
Eric Engestrom
0d74f4bb16 gbm: replace 1/0 bool with true/false
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-10-13 18:10:47 +01:00
Eric Engestrom
e9d8081135 gbm: turn 0/-1 bool into true/false
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-10-13 18:10:47 +01:00
Eric Engestrom
48289d8853 radv: add exported symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-13 17:40:54 +01:00
Eric Engestrom
960038d550 anv: add exported symbols check
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-13 17:40:47 +01:00
Eric Engestrom
f1c22390f7 symbols-check: ignore exported C++ symbols
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-13 17:40:43 +01:00
Boris Brezillon
35e92a11dd panfrost: Fix support for packed 24-bit formats
pan_pack_color() color was missing the 24-bit packed format case.
Looks like putting the clear color in a 32-bit slot does the trick.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-10-13 14:44:25 +02:00
Timothy Arceri
1294f01e06 glsl: fix crash compiling bindless samplers inside unnamed UBOs
The check to see if we were dealing with a buffer block was
too late and only worked for named UBOs.

Fixes: f32b01ca43 "glsl/linker: remove ubo explicit binding handling"

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1900
2019-10-12 22:04:23 +11:00
Neil Roberts
cece947a8d glsl/builtin: Add alternate versions of atan using new ops
Adds alternate versions of the atan builtin functions that use
ir_unop_atan and ir_binop_atan2 instead of inlining to the IR
implementation of the function. These alternatives are selected if the
IR is going to be consumed by NIR. In that case the IR ops will be
translated to the appropriate NIR op.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-12 09:43:18 +02:00
Neil Roberts
77f3fbb4aa glsl: Add opcodes for atan and atan2
Adds ir_binop_atan2 and ir_unop_atan. When converting to NIR these are
expanded out using the appropriate builtin generator. If they are used
with anything else then it will just hit an assert.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-12 09:43:18 +02:00
Neil Roberts
0832845dc6 nir/builtin: Add extern "C" guards to nir_builtin_builder.h
That way it can also be included from a C++ source.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-12 09:43:18 +02:00
Neil Roberts
9eaeedd54b nir/builtin: Add #include u_math.h to the header
The inline functions use M_PI so they should include a header to make
sure it is defined.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-12 09:43:18 +02:00
Neil Roberts
2098ae16c8 nir/builder: Move nir_atan and nir_atan2 from SPIR-V translator
Moves build_atan and build_atan2 into nir_builtin_builder. The goal is
to be able to use this from the GLSL translator too.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-10-12 09:43:17 +02:00
Hal Gentz
075a96aa92 egl: Configs w/o double buffering support have no EGL_WINDOW_BIT.
When users pass a config to `eglCreateWindowSurface` it requests double
buffering, but if the config doesn't have the appropriate `__DRIconfig`,
`eglCreateWindowSurface` fails with a `EGL_BAD_MATCH`.

Given that such behaviour is completely unacceptable, we drop the
`EGL_WINDOW_BIT` if we don't have at least one `__DRIconfig` supporting double
buffering, otherwise dropping the `EGL_PIXMAP_BIT`.

Fixes: 049f343e8a "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
2019-10-11 21:57:21 +00:00
Hal Gentz
a800d16e4f egl: Puts RGBA visuals in the second config selection group.
That way applications don't get windows that are compositor alpha-blended
accidentally.

In the ideal world, this would be done by the xserver, as it does for
GLX, however, an appropriate place could not be found, so it's being
placed here instead.

Fixes: 049f343e8a "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
2019-10-11 21:57:21 +00:00
Hal Gentz
90a19074b4 egl: Fixes transparency with EGL and X11.
This commit does this by allowing both RGB and RGBA visuals to match with
EGL configs. We also expose the `EGL_MESA_config_select_group` egl
extension, which is similar to GLX's visual select group extension, to
allow the RGBA visuals to get less priority.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Fixes: 049f343e8a "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
2019-10-11 21:57:21 +00:00
Hal Gentz
173bc9d684 egl: Add EGL_CONFIG_SELECT_GROUP_MESA ext.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676
Fixes: 049f343e8a "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Hal Gentz <zegentzy@protonmail.com>
2019-10-11 21:57:20 +00:00
Kenneth Graunke
44754279ac intel/fs/gen12: Use TCS 8_PATCH mode.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2019-10-11 12:24:16 -07:00
Jason Ekstrand
c92fb60007 intel/fs/gen12: Implement gl_FrontFacing on gen12+.
The bit moved on gen12 in order to prepare for dual-SIMD8 dispatch.
This implementation isn't an entirely complete as it only works on SIMD8
and SIMD16 and not dual-SIMD8.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Francisco Jerez
ceb123befa intel/fs/gen11+: Fix CS_OPCODE_CS_TERMINATE codegen.
Apparently the ts_request_type and ts_resource_select thread spawner
message descriptor bits were removed from the hardware at least since
ICL.  Drop them in order to avoid assertion failures on Gen12+
platforms which don't have any encoding for this.  On Gen9+ these are
probably just ignored by the hardware, so this is unlikely to have had
any functional implications prior to Gen12.

v2: Mark TS message fields as non-existing in brw_inst.h on ICL. (Caio)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-10-11 12:24:16 -07:00
Francisco Jerez
a5efb0eae8 intel/fs/gen12: Fix barrier codegen.
The WAIT instruction has been removed, but SYNC.bar can be used
instead to wait for a notification on n0.0.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Francisco Jerez
6b52f81395 intel/eu: Don't set notify descriptor field of gateway barrier message.
Apparently this field was removed on SKL, and according to the
hardware docs for previous platforms "This field is only valid for a
ForwardMsg message. It is ignored for other messages. The BarrierMsg
message always increments the N0 notification counter".

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Francisco Jerez
b0e69d115e intel/ir/gen12: Update assert in brw_stage_has_packed_dispatch().
Confirmed no regressions after a full Piglit run on TGL with the
brw_fs_test_dispatch_packing() test enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Jason Ekstrand
ca7b6fd392 intel/eu/validate/gen12: Don't blow up on indirect src0.
They look like a NULL source if you don't look at the address mode.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Francisco Jerez
ab5aa01689 intel/eu/validate/gen12: Validation fixes for SEND instruction.
The following fix-up by Jordan Justen is squashed in:

 intel/eu/validate: gen12 send instruction doesn't have a dst type field

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Francisco Jerez
a81f9b5e3e intel/eu/validate/gen12: Fix validation of SYNC instruction.
src0 will typically be null for this instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-11 12:24:16 -07:00
Francisco Jerez
45768e6b3c intel/eu/validate/gen12: Implement integer multiply restrictions in EU validator.
Due to hardware bug filed as HSDES#1604601757.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-10-11 12:24:16 -07:00