Commit graph

117072 commits

Author SHA1 Message Date
Boris Brezillon
296c5fd25d nir/lower_tex: Add a way to lower TXS(non-0-LOD) instructions
The V3D driver has an open-coded solution for this, and we need the
same thing for Panfrost, so let's add a generic way to lower TXS(LOD)
into max(TXS(0) >> LOD, 1).

Changes in v2:
* Use == 0 instead of !
* Rework the minification logic as suggested by Jason
* Assign cursor pos at the beginning of the function
* Patch the LOD just after retrieving the old value

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-18 06:36:07 -07:00
Boris Brezillon
0e489fd360 nir/lower_tex: Update ->sampler_dim value before calling get_texture_size()
get_texture_size() will create a txs instruction with ->sampler_dim set
to the original tex->sampler_dim. The condition to call lower_rect()
only checks the value of ->sampler_dim and whether lower_rect is
requested or not. This leads to an infinite loop when calling
nir_lower_tex() with the same options until it returns false.

In order to avoid that, let's move the tex->sampler_dim patching before
get_texture_size() is called. This way the txs instruction will have
->sampler_dim set to GLSL_SAMPLER_DIM_2D and nir_lower_tex() won't try
to lower it on the subsequent passes.

Changes in v2:
* Add Jason R-b
* Add a comment explaining why we patch ->sampler_dim at the beginning
  of the lower_rect() func

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-18 06:36:07 -07:00
Boris Brezillon
352b1d9c31 nir/lower_tex: Actually report when projector lowering happened
The code considers that projector lowering was done even if it's not
really the case. Change the project_src() prototype to return a bool
encoding whether projector lowering happened or not and update the
progress var accordingly in nir_lower_tex_block().

---
Changes in v2:
* Add Jason R-b
* Drop the part suggesting that nir_lower_rect() could be called in
  a do-while(progress) loop.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-18 06:36:07 -07:00
Tomeu Vizoso
6f60fec48f panfrost: Adapt to constant name change in UABI
We hadn't updated the kernel header after the driver got into mainline.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-18 15:26:08 +02:00
Tomeu Vizoso
5ad5777f89 panfrost: ci: Update results
Alyssa fixed some failing tests last night.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-18 15:25:01 +02:00
Samuel Pitoiset
c16bf48bfc radv: adjust the DCC base VA for mipmapped color attachments
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-18 12:24:26 +02:00
Samuel Pitoiset
6ee40efd02 radv: fix color decompressions for FMASK/CMASK
Only skip levels without DCC when it's a DCC decompression.
Whoops.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-18 12:09:04 +02:00
Samuel Pitoiset
42a41a9e4a radv: do not decompress levels without DCC with the graphics path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-18 11:24:50 +02:00
Samuel Pitoiset
e8917dcadb radv: do not decompress levels without DCC with the compute path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-18 11:24:41 +02:00
Samuel Pitoiset
864ddda8a3 radv: check if DCC is enabled per mip not for the whole image
In other words, make use of radv_dcc_enabled() instead of
radv_image_has_dcc() all over the places.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-18 11:24:36 +02:00
Iago Toral Quiroga
79a30543ee v3d: implement simultaneous peripheral access exceptions for V3D 4.1+
Shader-db results:

total instructions in shared programs: 9117550 -> 9102719 (-0.16%)
instructions in affected programs: 1752873 -> 1738042 (-0.85%)
helped: 7076
HURT: 478
helped stats (abs) min: 1 max: 22 x̄: 2.19 x̃: 2
helped stats (rel) min: 0.07% max: 13.89% x̄: 1.70% x̃: 1.07%
HURT stats (abs)   min: 1 max: 7 x̄: 1.41 x̃: 1
HURT stats (rel)   min: 0.09% max: 10.17% x̄: 0.86% x̃: 0.54%
95% mean confidence interval for instructions value: -2.00 -1.92
95% mean confidence interval for instructions %-change: -1.58% -1.50%
Instructions are helped.

total max-temps in shared programs: 1327774 -> 1327728 (<.01%)
max-temps in affected programs: 1025 -> 979 (-4.49%)
helped: 47
HURT: 2
helped stats (abs) min: 1 max: 2 x̄: 1.02 x̃: 1
helped stats (rel) min: 2.63% max: 20.00% x̄: 7.67% x̃: 5.26%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 4.17% max: 4.17% x̄: 4.17% x̃: 4.17%
95% mean confidence interval for max-temps value: -1.06 -0.82
95% mean confidence interval for max-temps %-change: -8.89% -5.49%
Max-temps are helped.

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-06-18 08:09:03 +02:00
Iago Toral Quiroga
6d97c8fac1 v3d: only flush jobs accessing the query BO when reading query results
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-06-18 08:09:03 +02:00
Iago Toral Quiroga
5491883a9a v3d: add a helper function to flush jobs using a BO
v2: use _mesa_set_search() (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-06-18 08:09:03 +02:00
Kenneth Graunke
e8cd7a30d5 iris: Support more RGBX pipe formats.
Without them, the state tracker falls back to an RGBA format, but it
doesn't always manage to override the swizzle for us.  So we lose the
information that the API expects an X channel, where alpha is garbage
and reads back as 1.  We have no equivalent ISL RGBX format for these,
so we just use RGBA directly and override the swizzle in all cases.
2019-06-17 21:52:38 -05:00
Kenneth Graunke
3c10a2726b glsl: Fix out of bounds read in shader_cache_read_program_metadata
The VaryingNames array has NumVaryings entries.  But BufferStride is
a small array of MAX_FEEDBACK_BUFFERS (4) entries.  Programs with
more than 4 varyings would read out of bounds.

Also, BufferStride is set based on the shader itself, which means that
it's inherently already included in the hash, and doesn't need to be
included again.  At the point when shader_cache_read_program_metadata
is called, the linker hasn't even set those fields yet.  So, just drop
it entirely.

Fixes valgrind errors in KHR-GL45.transform_feedback.linking_errors_test.

Fixes: 6d830940f7 glsl/shader_cache: Allow shader cache usage with transform feedback

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-06-17 21:22:19 -05:00
Jason Ekstrand
9672b7044c anv: Set STATE_BASE_ADDRESS upper bounds on gen7
This should fix floating-point border color on all gen7 HW.  Integer is
still thoroughly busted on gen7 because it doesn't exist on IVB and it's
crazy on HSW.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-06-17 18:53:07 -05:00
Bas Nieuwenhuizen
925c04b4c7 radv: Disable linear tiled compressed textures.
Support got removed in the new addrlib update.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-06-18 01:00:49 +02:00
Jason Ekstrand
1be38f9178 anv:Use VK_EXT_separate_stencil_usage to avoid stencil shadows on gen7
Whenever stencil texturing is not required (most of the time), we can
use VK_EXT_separate_stencil_usage to only create the shadow image when
VK_IMAGE_USAGE_SAMPLED_BIT is required for stencil.  Of course, this
depends on applications to use the extension but hopefully DXVK and
similar translators are doing so and that covers most of the apps.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-06-17 22:32:26 +00:00
Jason Ekstrand
f3ea0cf828 anv: Add stencil texturing support for gen7
Intel hardware didn't get support for sampling from W-tiled (required
for stencil) images until Broadwell so we can't directly sample from
stencil.  Instead, if we want to support stencil texturing on gen7
hardware, we have to keep a texture-capable shadow copy around and use
BLORP to update when stencil changes.  The one thing this commit does
not implement is self-dependencies with stencil input attachments.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99493
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-06-17 22:32:26 +00:00
Jason Ekstrand
4faa3145b1 anv/blorp: Update shadow images when clearing or uploading
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-06-17 22:32:26 +00:00
Jason Ekstrand
2b736d9e6c anv/cmd_buffer: Add a stencil transition helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-06-17 22:32:26 +00:00
Jason Ekstrand
86fc268142 anv/blorp: Take an aspect in anv_image_copy_to_shadow
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-06-17 22:32:26 +00:00
Jason Ekstrand
fcbefe013a anv/formats: Re-arrange the way se set some flag bits
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-06-17 22:32:26 +00:00
Kenneth Graunke
659d4f613e iris: Make resource_copy_region handle packed depth-stencil resources.
Also copy along the separate stencil buffer if needed.

Fixes Piglit's arb_copy_image-formats.
2019-06-17 17:29:09 -05:00
Kenneth Graunke
a36f1542ae iris: Order CS stall and TC invalidate for format reinterpretation hacks
This should ensure the TC invalidate happens after the stall.

Fixes KHR-GL43.copy_image.functional which does a CopyImage (blorp_copy)
from a buffer (using R8G8B8A8_UINT), then GetTexImage to read back the
original image (using R10G10B10A2_UNORM).
2019-06-17 16:38:08 -05:00
Kenneth Graunke
94b9f50e63 iris: Be more aggressive at post-format-reintepret TC invalidate hack
When copying/blitting with format reinterpretation, we invalidate the
texture cache before/after.  Before is so the source of the copy works,
and after is to get rid of our new data in the "wrong" format to protect
future attempts to sample.

When I ported these hacks to iris, I tried to be cautious by only
bothering with the hacks if the batch referenced the BO.  This makes
some sense for the before case.  If it isn't referenced, the texture
cache can't really have any data for the BO (since it's also invalidated
between batches).  But we still need to do the after case regardless,
as we've just polluted the cache with hazardous entries.
2019-06-17 16:38:08 -05:00
Gert Wollny
2b87753a84 virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts
When the host virglrenderer is an older version that doesn't check the sRGB write
control feature, or when the guest kernel doesn't support CAPS v2, then the guest
will only report support for GL 2.1 on a GL 3.3 host, even though it was supporting
3.3 with earlier guest mesa versions.

By also checking the host feature check version this regression can be avoided.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110921
Fixes: 2845939d6a
   virgl: Set sRGB write control CAP based on host capabilities

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-06-17 21:16:11 +00:00
Rob Clark
21c795ab07 freedreno/a6xx: disallow UBWC for x24s8
Fixes:
  dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d
  dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d
  dEQP-GLES31.functional.stencil_texturing.misc.compare_mode_effect

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-17 20:29:13 +00:00
Rob Clark
4e72abcd97 freedreno/a6xx: un-swap X24S8_UINT
The stencil is actually in the .w component, but we used to use SWAP to
remap the channels.  This doesn't work when tiled/ubwc.

Fixes:
  dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d_array
  dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_cube
  dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d_array
  dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube
  dEQP-GLES31.functional.stencil_texturing.misc.base_level
  dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_pot
  dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_npot
  dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot
  dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot
  dEQP-GLES31.functional.texture.border_clamp.sampler.uint_stencil

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-06-17 20:29:13 +00:00
Samuel Pitoiset
6e3aee4630 radv: add mipmaps support for DCC decompression on compute
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
ebb1db96d5 radv: add mipmaps support for color decompressions (DCC/FMASK/CMASK)
And some cleanups.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
00f0e5c6fd radv: set the DCC/FCE predicates from the base level
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
7832e75ea8 radv: load the fast color clear values from the base level
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
7971697efe radv: store the DCC predicate for each mip
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
38aa386e96 radv: store the FCE predicate for each mip
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
7295512037 radv: store the fast color clear values for each mip
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Samuel Pitoiset
58506fec63 radv: allocate DCC metadata for each mip
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 22:20:53 +02:00
Caio Marcelo de Oliveira Filho
4b0bc664a5 gallium: Remove unused util_ringbuffer
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-06-17 13:02:44 -07:00
Caio Marcelo de Oliveira Filho
397d1a18ef llvmpipe: Don't use u_ringbuffer for lp_scene_queue
Inline the ring buffer and signal logic into lp_scene_queue instead of
using a u_ringbuffer.  The code ends up simpler since there's no need
to handle serializing data from / to packets.

This fixes a crash when compiling Mesa with LTO, that happened because
of util_ringbuffer_dequeue() was writing data after the "header
packet", as shown below

    struct scene_packet {
       struct util_packet header;
       struct lp_scene *scene;
    };

    /* Snippet of old lp_scene_deque(). */
    packet.scene = NULL;
    ret = util_ringbuffer_dequeue(queue->ring,
                                  &packet.header,
                                  sizeof packet / 4,
    return packet.scene;

but due to the way aliasing analysis work the compiler didn't
considered the "&packet->header" to alias with "packet->scene".  With
the aggressive inlining done by LTO, this would end up always
returning NULL instead of the content read by
util_ringbuffer_dequeue().

Issue found by Marco Simental and iThiago Macieira.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110884
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-06-17 13:02:44 -07:00
Alyssa Rosenzweig
390126e70a panfrost/midgard: Simplify 2D array logic
It shouldn't matter if we stick a z in for non-arrays, anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 12:52:51 -07:00
Alyssa Rosenzweig
a3ae3cb8e9 panfrost/midgard: Handle non-zero component in store
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 12:52:51 -07:00
Alyssa Rosenzweig
2c9e124f81 panfrost/midgard: Apply writemask to LUTs
Fixes LUT instructions with NIR registers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 12:52:50 -07:00
Marek Olšák
eba932ea43 amd: update addrlib
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 15:14:55 -04:00
Nicolai Hähnle
d15cc1f55a radeonsi: reduce MAX_GEOMETRY_OUTPUT_VERTICES
This fixes piglit spec@glsl-1.50@gs-max-output on gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-17 15:14:51 -04:00
Alyssa Rosenzweig
aef01dd2e5 panfrost: Cleanup default blend mode
Just encode the Mali magic number for `replace` rather than awkwardly
forcing Gallium structures through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 10:45:52 -07:00
Alyssa Rosenzweig
fbbb29aa5b panfrost: Don't accidentally include blend shader
Some residual dirty state can leak through across frames; zero this out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 10:45:52 -07:00
Alyssa Rosenzweig
565c446dab panfrost/midgard: Use typeless moves internally
We switch all fmov to (i)mov, following the NIR switch. This simplifies
some code surrounding blend shaders and should have no functional
changes elsewhere.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-06-17 10:45:52 -07:00
Chia-I Wu
1fece5fa5f virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
When the resource to be mapped is busy and the backing storage can
be discarded, reallocate the backing storage to avoid waiting.

In this new path, we allocate a new buffer, emit a state change,
write, and add the transfer to the queue .  In the
PIPE_TRANSFER_DISCARD_RANGE path, we suballocate a staging buffer,
write, and emit a copy_transfer (which may allocate, memcpy, and
blit internally).  The win might not always be clear.  But another
win comes from that the new path clears res->valid_buffer_range and
does not clear res->clean_mask.  This makes it much more preferable
in scenarios such as

  access = enough_space ? GL_MAP_UNSYNCHRONIZED_BIT :
                          GL_MAP_INVALIDATE_BUFFER_BIT;
  glMapBufferRange(..., GL_MAP_WRITE_BIT | access);
  memcpy(...); // append new data
  glUnmapBuffer(...);

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00
Chia-I Wu
9975a0a84c virgl: add virgl_rebind_resource
We are going support reallocating the HW resource for a
virgl_resource.  When that happens, the virgl_resource needs to be
rebound to the context.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00
Chia-I Wu
7e0508d9aa virgl: save virgl_hw_res in virgl_transfer
When PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE is properly supported,
virgl_transfer might refer to a different virgl_hw_res than
virgl_resource does.  We need to save the virgl_hw_res and use the
saved one.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
2019-06-17 09:36:31 -07:00