Commit graph

1005 commits

Author SHA1 Message Date
Jason Ekstrand
89abfbeb7a nir: Disallow writes to system values and mem_constant
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6332>
2020-11-03 22:18:28 +00:00
Daniel Schürmann
bd0468ed33 nir: add options to lower nir_op_pack_[64/32]_* via nir_lower_alu_to_scalar()
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6527>
2020-10-28 10:14:26 +00:00
Ian Romanick
67956689bb nir: Rename replicated-result dot-product instructions
All these instructions replicate the result of a N-component dot-product
to a vec4.  Naming them fdot_replicatedN gives the impression that are
some sort of abstract dot-product that replicates the result to a vecN.
They also deviate from fdph_replicated... which nobody would reasonably
consider naming fdot_replicatedh.

Naming these opcodes fdotN_replicated more closely matches what they
are, and it matches the pattern of fdph_replicated.

I believe that the only reason these opcodes were named this way was
because it simplified the implementation of the binop_reduce function in
nir_opcodes.py.  I made some fairly simple changes to that function, and
I think the end result is ok.

The bulk of the changes come from the sed rename:

    sed --in-place -e 's/fdot_replicated\([234]\)/fdot\1_replicated/g' \
        $(grep -r 'fdot_replicated[234]' src/)

v2: Use a named parameter to binop_reduce instead of using
isinstance(name, str).  Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5725>
2020-10-22 18:00:19 +00:00
Eric Anholt
fdbc45d1d4 nir: Only validate in passes that might have changed things.
If a pass returning boolean progress reports no change, we shouldn't need
to re-validate.  If a pass breaks the NIR but also fails to report
progress correctly, it would be up to the next pass to catch that.

This should hopefully help with test timeouts on
KHR-GL33.texture_swizzle.functional since switching softpipe to
nir-to-tgsi and enabling NIR validation in CI (27s to 20s on my system).

Suggested-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7239>
2020-10-21 05:00:17 +00:00
Eric Anholt
d867e7c974 nir: Add an option to not lower source mods for f64/u64/i64.
TGSI can't handle them, but we want to use this pass for nir-to-tgsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3395>
2020-10-20 08:54:06 -07:00
Eric Anholt
c730feacc0 nir: Add a call to get a struct describing SSA liveness per instruction.
nir-to-tgsi will use this to release release temporaries for SSA storage
back to ureg's linear register allocation once they're dead.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3395>
2020-10-20 08:54:06 -07:00
Eric Anholt
a206b58157 nir: Add a block start/end ip to live instr index metadata.
I wanted it for the per-instruction live intervals metadata, and it's not
much to store in general.  Make the ip explicitly 32-bit, on suggestion by
jekstrand.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3395>
2020-10-20 08:54:06 -07:00
Eric Anholt
2f5d18403a nir: Replace nir_ssa_def->live_index with nir_instr->index.
live_index had two things going on: 0 meant the instr was an undef and
always dead, and otherwise ssa defs had increasing numbers by instruction
order.  We already have a field in the instruction for storing instruction
order, and ssa defs don't need that number to be contiguous (if you want a
compact per-ssa-def number, use ssa->index after reindexing).

We don't use ssa->index for this, because reindexing those would change
nir_print, and that would be rude to people trying to track what's
happening in optimization passes.

This openend up a hole in nir_ssa_def, so we move nir_ssa_def->index
toward the end to shrink the struct from 64 bytes to 56.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3395>
2020-10-20 08:54:01 -07:00
Eric Anholt
b6cb184e86 nir: Introduce nir_metadata_instr_index for nir_index_instr() being current.
This will be useful to remove the live_index field from nir_ssa_def.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3395>
2020-10-20 08:53:36 -07:00
Iago Toral Quiroga
6004ad9df1 nir/lower_io: add an option to lower interpolateAt functions
The option use_interpolated_input_intrinsics will lower these as well
as regular input loads. This is inconvenient for V3D, where we can
produce optimal code for regular input loads based on the input
variable layout qualifiers, so this change adds an option to only
lower instances of interpolateAt().

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6766>
2020-10-13 21:21:33 +00:00
Alejandro Piñeiro
10b79bf901 nir: include texture query lod as one of the ops that requires a sampler
In practice we found that we need this for v3d (specifically for cube
map arrays, as they don't support the default value for wrap_i, so a
sampler object is needed to override that value).

It is worth to note that the main reason behind this auxiliar method
was to identify those cases that we didn't have a sampler object
available for Vulkan. So far, we found that we have a sampler object
coming from nir always for that operation.

Fixes cube map array tests like the following:
dEQP-VK.glsl.texture_functions.query.texturequerylod.usamplercubearray_fragment

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6766>
2020-10-13 21:21:31 +00:00
Rhys Perry
f83bc5beb8 nir: add pass to optimize uniform atomics
This optimizes atomics with a uniform offset so that only one atomic
operation is done in the subgroup.

For shaders which do a very large amount of atomics, this can
significantly improve performance.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6558>
2020-10-13 12:47:21 +00:00
Rhys Perry
37b6b0967c nir: allow divergence information to be updated when inserting instruction
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6558>
2020-10-13 12:47:21 +00:00
Rhys Perry
e1120f274f nir: move divergence analysis options to nir_shader_compiler_options
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6558>
2020-10-13 12:47:21 +00:00
Rhys Perry
8850a63161 radv/aco,nir/lower_subgroups: don't lower elect
ACO can implement this better.

fossil-db (Navi):
Totals from 33 (0.02% of 135946) affected shaders:
SGPRs: 1736 -> 1744 (+0.46%)
VGPRs: 1680 -> 1656 (-1.43%)
CodeSize: 246160 -> 245916 (-0.10%); split: -0.14%, +0.04%
MaxWaves: 449 -> 461 (+2.67%)
Instrs: 48301 -> 48266 (-0.07%); split: -0.12%, +0.05%
Cycles: 469740 -> 469240 (-0.11%); split: -0.18%, +0.08%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6558>
2020-10-13 12:47:20 +00:00
Jose Maria Casanova Crespo
e7127b3468 nir/algebraic: optimize iand/ior of (n)eq zero when umax/umin not available
Before 8e1b75b330 ("nir/algebraic: optimize iand/ior of (n)eq zero") this
optimization didn't need the use of umax/umin. VC4 HW supports only signed
integer max/min operations.

lower_umin and lower_umax are added to allow enabling previous optimizations
behaviour for this cases.

Fixes: 8e1b75b330 ("nir/algebraic: optimize iand/ior of (n)eq zero")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7083>
2020-10-10 13:16:37 +02:00
Rhys Perry
5f2671bcc5 nir: return progress from nir_lower_io_to_scalar_early
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6891>
2020-10-09 15:47:59 +00:00
Timur Kristóf
f11f4a2a4d nir: Add ability to count primitives per stream.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6964>
2020-10-09 15:26:14 +02:00
Timur Kristóf
aac5adc3c2 nir: Count vertices per stream.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6964>
2020-10-09 15:26:14 +02:00
Timur Kristóf
70b94adddb nir: Add ability to overwrite incomplete GS primitives.
After each end_primitive and at the end of the shader before emitting
set_vertex_and_primitive_count, we check if the primitive that is being
emitted has enough vertices or not, and we adjust the vertex and
primitive counters accordingly.

As a result, if the backend uses this option, the backend compiler
will not have to worry about discarding the unneeded vertices
and primitives.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6964>
2020-10-09 15:26:14 +02:00
Timur Kristóf
c977c369d3 nir: Add ability to count emitted GS vertices per primitive.
Add an option to nir_lower_gs_intrinsics so that it can also track
the number of emitted vertices per primitive, not just the total
vertex count.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6964>
2020-10-09 15:26:14 +02:00
Timur Kristóf
2be99012e9 nir: Add ability to count emitted GS primitives.
Add an option to nir_lower_gs_intrinsics which tells it to track
the number of emitted primitives, not just vertices. Additionally,
also make it per-stream.

Also rename the set_vertex_count intrinsic to
set_vertex_and_primitive_count.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6964>
2020-10-09 15:26:14 +02:00
Kristian H. Kristensen
826a10255f st/mesa: Add NV12 lowering to PIPE_FORMAT_R8_G8B8_420_UNORM
Some GPUs can sample biplanar formats like NV12 natively, returning
the YUV values. Add a lowering type that uses that for sampling and
relies on existing colorspace conversions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6693>
2020-10-08 09:37:14 +00:00
Marek Olšák
3f1b35a2f0 nir: add new helper passes that lower uniforms to literals
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6955>
2020-10-07 17:30:12 +00:00
Marek Olšák
1e7d82c881 nir/algebraic: always lower idiv to shifts if bitops are allowed
why would you want anything else

The only platform significantly affected by this is Intel where `lower_idiv`
is not set today but neither is `lower_bitops`.  There it seems to still be
a boon over-all.

Shader-db results on Ice Lake:

    total instructions in shared programs: 19719051 -> 19735766 (0.08%)
    instructions in affected programs: 106992 -> 123707 (15.62%)
    helped: 0
    HURT: 445
    HURT stats (abs)   min: 3 max: 295 x̄: 37.56 x̃: 44
    HURT stats (rel)   min: 0.16% max: 33.33% x̄: 19.60% x̃: 19.38%
    95% mean confidence interval for instructions value: 33.60 41.53
    95% mean confidence interval for instructions %-change: 18.97% 20.23%
    Instructions are HURT.

    total loops in shared programs: 5973 -> 5973 (0.00%)
    loops in affected programs: 0 -> 0
    helped: 0
    HURT: 0

    total cycles in shared programs: 489405810 -> 486917482 (-0.51%)
    cycles in affected programs: 4759097 -> 2270769 (-52.29%)
    helped: 406
    HURT: 34
    helped stats (abs) min: 2 max: 64661 x̄: 6291.95 x̃: 3126
    helped stats (rel) min: 0.02% max: 79.42% x̄: 43.32% x̃: 55.83%
    HURT stats (abs)   min: 2 max: 29376 x̄: 1947.12 x̃: 30
    HURT stats (rel)   min: 0.04% max: 23.82% x̄: 4.66% x̃: 1.33%
    95% mean confidence interval for cycles value: -6753.06 -4557.52
    95% mean confidence interval for cycles %-change: -42.60% -36.63%
    Cycles are helped.

    total spills in shared programs: 12481 -> 12482 (<.01%)
    spills in affected programs: 47 -> 48 (2.13%)
    helped: 0
    HURT: 1

    total fills in shared programs: 12816 -> 12819 (0.02%)
    fills in affected programs: 71 -> 74 (4.23%)
    helped: 0
    HURT: 1

    total sends in shared programs: 1010124 -> 1010124 (0.00%)
    sends in affected programs: 0 -> 0
    helped: 0
    HURT: 0

    LOST:   1
    GAINED: 0

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6963>
2020-10-07 10:50:53 -04:00
Jason Ekstrand
b2e1fc8976 nir: Add a pass to lower vec3s to vec4s
LLVM loves take advantage of the fact that vec3s in OpenCL are 16B
aligned and so it can just read/write them as vec4s.  This results in a
LOT of vec4->vec3 casts on loads and stores.  One solution to this
problem is to get rid of all vec3 variables.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>
2020-10-02 07:30:49 +00:00
Jason Ekstrand
769ede2de4 nir: Add component mask re-interpret helpers
These are based on the ones which already existed in the load/store
vectorization pass but I made some improvements while moving them.  In
particular,

 1. They're both faster if the bit sizes are equal
 2. The check is faster if old_bit_size > new_bit_size
 3. The check now fails if it would use more than NIR_MAX_VEC_COMPONENTS

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>
2020-10-02 07:30:49 +00:00
Jason Ekstrand
f6667cb0ce nir: Add a memcpy optimization pass
This pass attempts to optimize three broad categories of memcpy:

 1. Self-copies: These we can discard out-of-hand.

 2. Vector copies: It doesn't matter what the vector size is or if the
    source and destination have different vector types, it's still easy
    enough to emit a load/store pair.

 3. Tightly packed copies:  In the case where a type is tightly packed
    (no padding bits), we can replace the memcpy with a copy_deref
    instruction which the optimizer is far better at handling.

This has proven capable of getting rid of many of the memcpy instances
in some rather gnarly OpenCL C kernels I've been looking at, even after
coming out of LLVM's optimizer.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>
2020-10-02 07:30:49 +00:00
Jason Ekstrand
98bb74b67d nir: Fix a misspelling
Fixes: cb95065dd1 "nir: Add lowering from regular ALU conversions..."
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6975>
2020-10-01 20:44:04 -05:00
Jason Ekstrand
cb95065dd1 nir: Add lowering from regular ALU conversions to the intrinsic
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>
2020-10-01 18:36:53 +00:00
Jason Ekstrand
383ecfbc70 nir: Add a passes for nir_intrinsic_convert_alu_types
This adds primarily two passes:  One is a lowering pass which turns
these conversion intrinsics into a series of ALU ops.  The other is an
optimization pass which attempt to simplify the conversion whenever
possible in the hopes that we can turn it into a "normal" conversion op
which doesn't need special treatment.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>
2020-10-01 18:36:53 +00:00
Jason Ekstrand
588bb6686b nir: Add a conversion and rounding intrinsic
This new intrinsic is capable of handling the full range of conversions
from OpenCL including rounding modes and possible saturation.  The
intention is that we'll emit this intrinsic directly from spirv_to_nir
and then lower it to ALU ops later.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>
2020-10-01 18:36:53 +00:00
Jason Ekstrand
0aa08ae2f6 nir: Split NIR_INTRINSIC_TYPE into separate src/dest indices
We're about to introduce conversion ops which are going to want two
different types.  We may as well just split the one we have rather than
end up with three.  There are a couple places where this is mildly
inconvenient but most of the time I find it to actually be nicer.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>
2020-10-01 18:36:53 +00:00
Eric Anholt
618556a8cb nir: Drop the high_offset argument to the load_store_vectorizer filter.
Nothing uses it, and it's not clear to me what it provides over
alignment/num_components/bit_size.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6612>
2020-09-30 19:53:43 +00:00
Eric Anholt
5f757bb95c nir: Make the load_store_vectorizer provide align_mul + align_offset.
It was passing an encoding of the two that wasn't good for ensuring "Don't
combine loads that would make us straddle a vec4 boundary" for
nir_lower_ubo_vec4.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6612>
2020-09-30 19:53:43 +00:00
Eric Anholt
6c1c571440 nir: Document a bit about how align_mul/offset work.
Introduces a #define for the maximum valid align_mul that's used in the
load_store_vectorizer tests (currently, though it will be used more soon).

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6612>
2020-09-30 19:53:43 +00:00
Jason Ekstrand
ac7537f155 nir/lower_io: Add support for push constants
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5275>
2020-09-30 07:20:38 +00:00
Connor Abbott
bc8a5c0752 nir: Add per_view to IO semantics
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6514>
2020-09-29 10:32:00 +00:00
Connor Abbott
ffe946d7e8 nir: Add nir_lower_multiview pass
Taken mostly directly from the anv pass. A few anv-specific things that
I could leave in anv aren't included. Specifically on turnip we don't
need to set gl_Layer to 0, and we can handle the case where the FS reads
gl_ViewIndex, so that check is moved into anv.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6514>
2020-09-29 10:31:59 +00:00
Samuel Pitoiset
a0e35c7562 nir/lower_io: change nir_io_add_const_offset_to_base to use bitfield modes
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6890>
2020-09-29 09:40:21 +00:00
Jason Ekstrand
a3177cca99 nir: Add a lowering pass to lower memcpy
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6713>
2020-09-25 23:48:03 +00:00
Jesse Natalie
93db59e066 nir: Add an internal flag to shader_info
Don't print the shader if it's marked internal, unless NIR_PRINT
has been explicitly set to 2 (or higher).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6035>
2020-09-25 20:09:08 +00:00
Kenneth Graunke
140f53e646 Revert "nir: replace lower_ffma and fuse_ffma with has_ffma"
This reverts commit 939ddf3f67.

Intel has a separate pass for fusing FFMAs selectively.  We split
these flags in commit 1b72c31e1f and
the reasoning still stands.  The patch being reverted was just a
cleanup, so there should be no issue with reverting it.

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6849>
2020-09-24 13:11:50 -07:00
Marek Olšák
939ddf3f67 nir: replace lower_ffma and fuse_ffma with has_ffma
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
2020-09-24 12:29:11 +00:00
Marek Olšák
771aad3027 nir: split lower_ffma into lower_ffma16/32/64
AMD wants different behavior for each bit size

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
2020-09-24 12:29:11 +00:00
Marek Olšák
21174dedec nir: split fuse_ffma into fuse_ffma16/32/64
AMD wants different behavior for each bit size

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6756>
2020-09-24 12:29:11 +00:00
Jason Ekstrand
e1fc23265f nir: Add a pass for lowering CL-style image ops to texture ops
In CL 1.2, images are required to be either read-only or write-only.  We
can always translate the read-only image ops to texture ops.  In CL 2.0
(and an extension), the ability is added to have read-write images but
sampling (with a sampler) is only allowed on read-only images.  As long
as we only lower read-only images to texture ops, everything should stay
consistent.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6578>
2020-09-20 14:28:13 +00:00
Gert Wollny
2c9fee9b6a nir: Add option lower_uniforms_to_ubo
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6316>
2020-09-16 10:07:42 +00:00
Marek Olšák
c2ae39e0ce nir: add mediump flag to IO semantics
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6621>
2020-09-10 19:52:57 +00:00
Jesse Natalie
7ee5da90ed nir_dominance: Use uint32_t instead of int16_t for dominance counters
We're seeing OpenCL kernels that can hit this INT16_MAX block count.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6657>
2020-09-09 19:01:01 +00:00