Commit graph

98299 commits

Author SHA1 Message Date
Marek Olšák
373f4a48ae radeonsi: implement fast color clear for DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák
36ac7a1b0e radeonsi: add a workaround for blending with DCC and MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák
d1f65e5e99 radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák
e3c0a5b6e8 ac/surface: enable DCC computation for MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Marek Olšák
6863651bbd radeonsi: fix layered DCC fast clear
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 18:21:30 +01:00
Jon Turney
2c62ccb10a util: Also include endian.h on cygwin
If u_endian.h can't determine the endianess, the default behaviour in sha1.c
is to build for big-endian

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-11-29 14:04:40 +00:00
Juan A. Suarez Romero
6d540aa092 mesa: deal with vs_inputs as 64-bit unsigned integer
Commit 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") uses
vs_prog_data->vs_inputs as if it were a 32-bit unsigned integer.

But actually it is a 64-bit integer, and as such it is used in other
parts of Mesa code. It is worth to note that bits from the entire range
are used, and not only 32-bits. This is due our implementation for
handling 64-bit dual-slot input attributes, which requires to use a
larger bitfield to manage them.

This commit reverts the changes done in brw_draw_upload.c, keeping the
rest of the changes.

This fixes the following tests:

- KHR-GL45.enhanced_layouts.varying_array_locations
- KHR-GL45.enhanced_layouts.varying_locations

Fixes: 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103942
CC: Marek Olšák <marek.olsak@amd.com>
CC: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-11-29 12:13:10 +01:00
Timothy Arceri
a39a3b4b76 mesa: rework _mesa_add_parameter() to only add a single param
This is more inline with what the functions name suggests it should
do, and makes the code much easier to follow.

This will also make adding uniform packing support much simpler.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-11-29 21:50:48 +11:00
Dave Airlie
f8a54c489d r600: lds load cleanups.
This is just some cleanups on top of the last patch from my compute branch.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-29 13:18:44 +10:00
Gert Wollny
76837e29e3 r600_shader: only load from LDS what is really used
Use the destination write mask to determine which values are really to be
read from LDS and load only these.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
2017-11-29 13:08:29 +10:00
Dave Airlie
579ec9c311 r600/sb: handle jump after target to end of program. (v2)
This fixes hangs on cayman with
tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test

This has a single if/else in it, and when this peephole activated,
it would set the jump target to NULL if there was no instruction
after the final POP. This adds a NOP if we get a jump in this case,
and seems to fix the hangs, so we have a valid target for the ELSE
instruction to go to, instead of 0 (which causes infinite loops).

v2: update last_cf correctly. (I had some other patches hide this)

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-11-29 11:52:53 +10:00
Kenneth Graunke
6b91610fc6 i965: Change a ret == -1 check to ret != 0.
For consistency with most other ret checks.  Suggested by Chris.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-11-28 15:23:16 -08:00
Kenneth Graunke
874d41add3 i965: Use C99 struct initializers in brw_bufmgr.c.
This is cleaner than using a non-standard memclear macro (which does a
memset to 0) and then initializing fields after the fact.  We move the
declarations to where we initialized the fields.  While we're at it, we
move the declaration of 'ret' that goes with the ioctl, eliminating the
declaration section altogether.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-11-28 15:23:16 -08:00
Kenneth Graunke
3d68329a65 i965: Move perf_debug and WARN_ONCE back to brw_context.h.
These were moved to src/intel/common/gen_debug.h, but they are not
common code.  They assume that brw_context or gl_context variables
exist, named brw or ctx.  That isn't remotely true outside of i965.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-11-28 15:23:16 -08:00
Eric Engestrom
07d3966694 i965: const a few structs and vars to avoid writing to them by accident
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 15:23:16 -08:00
Kenneth Graunke
760e0156df i965: Fix Smooth Point Enables.
We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.

Fixes: 13ac46557a (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-11-28 15:23:16 -08:00
Dylan Baker
43b0e5f5cd meson: build virgl driver
Build tested only.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 14:06:38 -08:00
Dylan Baker
a537231b22 meson: build svga driver on linux
Build tested only.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 14:06:36 -08:00
Dylan Baker
5060c51b6f meson: build r600 driver
v4: - Ensure inc_amd_common defined when radeonsi is disabled (needed by
      r600)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 14:06:33 -08:00
Dylan Baker
4ae08296d0 meson: build r300 driver
This is build tested only

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 14:06:30 -08:00
Dylan Baker
9169dde941 meson: build i915g driver
Build tested only.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 14:06:26 -08:00
Brian Paul
c5d199fa2c svga: move svga_is_format_supported() to svga_format.c
where the other format-related functions live.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-28 06:50:16 -07:00
Brian Paul
bae5b2a87c svga: s/unsigned/SVGA3dDevCapIndex/
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-11-28 06:50:16 -07:00
Lionel Landwerlin
addfa4c5e8 i965: perf: add support for CoffeeLake GT3
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
b5f6b9b0eb i965: perf: add support for CoffeeLake GT2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
74f41fd781 i965: perf: add busyness metric sets on gen8/9 platforms
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
a543ae4c2a i965: fix time elapsed counter equations in VME/Media configs
There was a mistake just in those metric sets. We probably didn't
noticed because they're not really interesting for 3D workloads.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
064a4831e3 i965: perf: update counter names on gen8/9 platforms
Just fixing names.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
349712018b i965: add a debug option to disable oa config loading
This provides a good way to verify we haven't broken using the perf
driver on older kernels (which don't have the oa config loading
mechanism).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
27ee83eaf7 i965: perf: add support for userspace configurations
This allows us to deploy new configurations without touching the
kernel.

v2: Detect loadable configs without creating one (Chris)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Lionel Landwerlin
3e7112e603 i965: perf: update configs for loading from userspace
When making configs loadable from userspace in the kernel, we left to
userspace more responsability around programming some registers. In
particular one register we use to set directly in the driver has now
been moved into the configs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-11-28 13:34:04 +00:00
Eric Engestrom
44fbbd6fd0 util: add mesa-sha1 test to meson
Fixes: 513d7ffa23 "util: Add a SHA1 unit test program"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-11-28 11:06:04 +00:00
Eric Engestrom
9d281e1506 compiler: fix typo
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-11-28 10:54:38 +00:00
Eric Engestrom
7b85b9b877 compiler: use NDEBUG to guard asserts
nir_validate.c's #endif already had the correct NDEBUG comment

Fixes: dcb1acdea0 "nir/validate: Only build in debug mode"
Fixes: 9ff71b649b "i965/nir: Validate that NIR passes call nir_metadata_preserve()"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-11-28 10:54:38 +00:00
Eric Engestrom
bb46111c01 broadcom: use NDEBUG to guard asserts
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 09:50:36 +00:00
Eric Engestrom
7bb89e1c8f vc4: check preprocessor token existence using #ifdef instead of #if
(other uses of USE_VC4_SIMULATOR are already correct)

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-11-28 09:50:36 +00:00
Ben Crocker
b43daf7bf6 docs/llvmpipe.html: Minor edits
Language and spelling fixups in three places.

Cc: "17.2" "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

[Eric: move two fixes from the other patch to this one.]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-11-28 09:50:36 +00:00
Eric Engestrom
bca122902a st/dri: replace hard-coded array size with ARRAY_SIZE()
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:50:36 +00:00
Nicolai Hähnle
dd07868904 radeonsi/gfx9: simplify condition for on-chip ESGS
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
239d2b5809 radeonsi: clarify that si_shader_selector::esgs_itemsize is set for the ES part
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
26da5d0317 radeonsi: use si_shader_context instead of lp_build_context in more places
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
1c2d19d84d radeonsi: cleanup si_initialize_color_surface
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
08f6b4dd7b radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have it
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
e52e8326d9 radeonsi: check that we don't leak fine.buf references
Just as an added precaution.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
377a062321 ac/surface: fix indentation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
97f42d11df amd/common: sid.h cleanups
Fix a bunch of labels indicating when registers were added/removed
and normalize the SI-class GRBM_GFX_INDEX.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:34:43 +01:00
Nicolai Hähnle
7e35bdad1c st_glsl_to_tgsi: check for the tail sentinel in merge_two_dsts
This fixes yet another case where DFRACEXP has only one destination. Found
by address sanitizer.

Fixes tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4-only-mantissa.shader_test

Fixes: 3b666aa747 ("st/glsl_to_tgsi: fix DFRACEXP with only one destination")
Acked-by: Marek Olšák <marek.olsak@amd.com>
2017-11-28 09:31:33 +01:00
Tapani Pälli
1e508e10d9 mesa/gles: adjust internal format in glTexSubImage2D error checks
When floating point textures are created on OpenGL ES 2.0, driver
is free to choose used internal format. Mesa makes this decision in
adjust_for_oes_float_texture. Error checking for glTexImage2D properly
checks that sized formats are not used. We use same error checking
path for glTexSubImage2D (since there is lot of overlap), however since
those checks include internalFormat checks, we need to pass original
internalFormat passed by the client. Patch adds oes_float_internal_format
that does reverse adjust_for_oes_float_texture to get that format.

Fixes following test failure:
   ES2-CTS.gtf.GL2ExtensionTests.texture_float.texture_float

(when running test with MESA_GLES_VERSION_OVERRIDE=2.0)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103227
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-11-28 08:57:49 +02:00
Jason Ekstrand
049b84246e radv: Use the suffixed versions of VK_QUEUE_GLOBAL_PRIORITY_*
Acked-by: Dave Airlie <airlied@redhat.com>
2017-11-27 21:42:06 -08:00
Jason Ekstrand
07850893a1 vulkan: Update the XML and headers to 1.0.66
Acked-by: Dave Airlie <airlied@redhat.com>
2017-11-27 21:41:46 -08:00