[HOW]
- Re-order the function pointer assignments to have the same order as
defined.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-Off-by: Navid Assadian <Navid.Assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
The packet header has uninitialized fields that can introduce 1b'1 in
reserved bits.
[HOW]
initialize the header to 0
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Roy Chan <Roy.Chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Multiplication result may overflow int before it is converted to long
long
[HOW]
Updated the expression to avoid possible overflow
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Support different generations of swizzle mode.
[HOW]
Added different swizzle mode parameters for supporting plane
description.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Ricky Lin <Ricky.Lin@amdeng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Fast load support is required for 3DLUT and Shaper features.
The calculation logic needs to be modularized and exposed via
the resource interface to support this.
[HOW]
1. Add `calculate_shaper` and `program_fastload` function pointers to the `resource` struct.
2. Move shaper normalization, HDR multiplier update, and 3DLUT update logic from
`vpe_color_update_movable_cm` into a new core function `vpe_calculate_shaper`.
3. Implement `vpe10_calculate_shaper` and assign it to the resource function table for VPE10 and VPE11.
4. Update `vpe_create_engine` return signature to remove `const` qualifier.
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
[WHY]
Reg_update macro and its lastWritten_value design are static global
variables and cannot support multi-thread usage
[HOW]
remove reg_update usage and combine the separated calls together
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
This is necessary for GetPipelineExecutablePropertiesKHR, RADV_DEBUG and
fossil-db.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39827>
Having them in GTT makes read back fast but it also affects performance
a lot. Now that a staging buffer can be used for read back, we can
switch to VRAM without drawbacks.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
pipe_aligned_buffer_create can allow allocate 4GB but that's large enough
for now.
PIPE_USAGE_STREAM is used for now to keep the 2 BOs in GTT.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
This will allow to use a staging buffer to copy the sqtt data
without moving away the BO from VRAM (without this change,
the vram->staging copy won't be executed since we're in the
middle of a flush).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
Given a situation like this :
- CB_A: begin, renderDepthA, end
- CB_B: begin, computeA, barrier (depth), computeB, end
The depth cache is not being flushed between renderDepthA & computeB
because :
- it's not flushed at the end of CB_A (it's not required)
- when CB_B starts, we're still on GFX pipeline mode but do not
flush render caches because pipeline mode is unknown
- when barrier is CB_B is executed, we're already in compute
pipeline mode and HW cannot flush depth.
The fix is to flush RT/depth cached when switching from unknown
pipeline mode any pipeline mode.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e6dae6ef5f ("vulkan: Optimize implicit end_subpass barrier")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14816
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: David Gow <david@davidgow.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39824>
Now that we have a solid logic for caching meta objects, trying to
reduce the number of format variants isn't super useful. In practice,
the shaders would be cached on disk, so this would only allocate few
more bytes for the meta objects.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39786>
The Vulkan spec says:
"Store and resolve operations are only performed at the end of a
render pass instance that does not specify the
VK_RENDERING_SUSPENDING_BIT_KHR flag."
VK_RENDERING_SUSPENDING_BIT is also illegal with custom resolves.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
This is mostly for not calling CmdBeginRendering() while rendering
is already active in order to catch potential driver issues. This
requires a small refactoring of how the rendering info is passed for
resolves though.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
This bit is set in mocs for other protected attachment types by
anv_image_fill_surface_state() however was ommited for depth/stencil
attachments here.
Without the protected bit set, it causes heavy black artifacting when
attaching a protected depth attachment image to a framebuffer.
Fixes: 794b0496e9 ("anv: enable protected memory")
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39818>
The Panfrost hardware already supports controlling ASTC decode
precision via the Decode Wide plane descriptor field. Wire up the
Vulkan extension by parsing VkImageViewASTCDecodeModeEXT from the
image view pNext chain and setting astc.narrow when the application
requests VK_FORMAT_R8G8B8A8_UNORM decode mode.
The extension is limited to v9+ since the ASTC plane descriptors
with Decode Wide/HDR fields only exist from Valhall onwards.
decodeModeSharedExponent is not supported.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39799>
The destination for CmdResolve can be a 3D image, and while some
restrictions on the base layer and count exist, the Z offset into which
the resolve will happen has no such restriction.
Fixes some new tests: dEQP-VK.pipeline.*.multisample.m10_resolve.resolve_cmd.*.full_3d.*
Fixes: 0e7761b35cd ("anv, hasvk: allow using a 3D image as a resolve target")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39793>
`operands_match` was modifying instruction source operands in-place
(through the `elk_fs_reg *src` pointer member) and relying on a
save/restore pattern to undo the modifications. Work on local copies
instead, which is simpler and avoids mutating shared state in a
comparison function.
Fixes: 47c4b38540 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39814>
The MUL case in `operands_match` was reading and writing the `.f` union
member unconditionally, even when the register's `.file != IMM`. In that
case `.f` aliases the struct containing `.nr`/`.swizzle`/etc, so the
`fabsf()` call could corrupt the `.nr` by clearing bit 31.
Guard all `.f` accesses with `.file == IMM` checks.
Fixes: 47c4b38540 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39814>
`operands_match` was modifying instruction source operands in-place
(through the `brw_reg *src` pointer member) and relying on a
save/restore pattern to undo the modifications. Work on local copies
instead, which is simpler and avoids mutating shared state in a
comparison function.
Fixes: 47c4b38540 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39814>
The MUL case in `operands_match` was reading and writing the `.f` union
member unconditionally, even when the register's `.file != IMM`. In that
case `.f` aliases the struct containing `.nr`/`.swizzle`/etc, so the
`fabsf()` call could corrupt the `.nr` by clearing bit 31.
Guard all `.f` accesses with `.file == IMM` checks.
Fixes: 47c4b38540 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39814>
Could do better by checking which registers are clobbered/preserved,
but that's unlikely to be useful anyway.
Backport-to: 26.0
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39801>
All other drivers in mesa report NIR for
VK_KHR_pipeline_executable_properties let's do the same as this can be
useful to see what we have right before compilation.
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39772>
I somehow screwed this up on my previous attempt at fixing this bug,
This should fix the loop limiter bug on big endian properly.
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: mesa-stable
Fixes: e28cfb2bad ("gallivm: handle u8/u16 const loads properly on big-endian.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39813>
