Commit graph

872 commits

Author SHA1 Message Date
Alyssa Rosenzweig
d50d9eccad ac,radv,radeonsi: use common 1D texture lowering
It was pulled from ac.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26397>
2023-11-29 14:04:15 +00:00
Connor Abbott
0d186d356c amd: Enable boolean subgroup lowering
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/218>
2023-11-17 09:45:40 +00:00
Tatsuyuki Ishi
538ca7801a radv: Use shader part caching helpers for VS prolog and PS/TCS epilog.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028>
2023-11-14 13:45:22 +00:00
Tatsuyuki Ishi
611545fbfe radv: Implement helpers for shader part caching.
Currently, shader part caching logic is duplicated between VS prolog and
PS/TCS epilogs. This commit introduces a common abstraction to
deduplicate the code.

Additionally, there are a few design decisions that diverts from the
current implementation:
1. A simple mutex is used instead of reader-writer lock. Prolog/epilog
   constructions are serialized, removing the need to free duplicate
   objects in case of a race.
2. A CS-local cache is used to quickly lookup an entry without holding a
   lock. This eliminates locking in over 99% of cases.
3. A set is used to reduce number of allocations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26028>
2023-11-14 13:45:22 +00:00
Tatsuyuki Ishi
55d21f2f12 radv, aco: Inline struct aco_vs_input_state.
Now that we no longer use the radv_vs_input_state pointer, we can simply
inline all the state-related fields.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
2023-11-13 11:47:42 +00:00
Tatsuyuki Ishi
3fc3a94bce radv, aco: Rework VS prolog key handling.
The main change is to use struct radv_vs_prolog_key directly instead of
the compressed representation to simplify an upcoming rework in prolog /
epilog caching. In doing so the state struct pointer was replaced with
an inline struct.

Care was also taken to pre-mask all the states with the active attribute
mask and other masks when it makes sense; this ensures that we don't
accidentally use information not hashed into the key during compilation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26023>
2023-11-13 11:47:42 +00:00
Rhys Perry
7de34ad3ef radv: use NIR_LOOP_PASS helpers
A somewhat random collection of fossils:
    N           Min           Max        Median           Avg        Stddev
x   6         16.59         16.61        16.605     16.603333  0.0081649658
+   6         15.99            16            16     15.998333  0.0040824829
Difference at 95.0% confidence
	-0.605 +/- 0.00830327
	-3.64385% +/- 0.0485573%
	(Student's t, pooled s = 0.00645497)

I'm not sure if nir_opt_if and nir_opt_loop_unroll are actually idempotent
or not.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24197>
2023-11-01 14:16:37 +00:00
Mike Blumenkrantz
c4283e32e3 radv: correctly return oom from the device when failing to create a cs
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25927>
2023-10-27 15:29:32 +00:00
Faith Ekstrand
d5c310899a nir: Split nir_lower_subgroup_options::lower_vote_eq into two bits
On NVIDIA, we can do a vote_ieq on bool in one hardware op so we don't
want that lowered.  We do want to lower vote_feq and other vote_ieq,
though.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25894>
2023-10-26 23:05:44 +00:00
Rhys Perry
c29d8a9e68 ac/nir,radv: pass workgroup size to ac_nir_lower_ngg_ms
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25040>
2023-10-24 21:36:06 +00:00
Rhys Perry
23cb0b00db radv: implement mesh shader gs_fast_launch=2
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25040>
2023-10-24 21:36:06 +00:00
Rhys Perry
cddbe9a4c2 ac/nir: implement mesh shader gs_fast_launch=2
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25040>
2023-10-24 21:36:06 +00:00
Samuel Pitoiset
f9cc2c5ba4 Revert "radv: fix finding shaders by PC"
Shaders are no longer allocated contiguously in memory and the next
pointer is now the shader.

This fixes using the trap handler on GFX8.

This reverts commit 2dcd12f38b.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25852>
2023-10-24 14:19:13 +00:00
Bas Nieuwenhuizen
9df4703fbb radv: Add cooperative matrix lowering.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24683>
2023-10-24 13:24:18 +00:00
Rhys Perry
99214f0481 radv: skip zero-sized memcpy
Fixes UBSan:
src/amd/vulkan/radv_pipeline.c:1181:4: runtime error: null pointer passed as argument 2, which is declared to never be null
src/amd/vulkan/radv_shader.c:2243:4: runtime error: null pointer passed as argument 2, which is declared to never be null

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25432>
2023-10-23 22:16:26 +00:00
Qiang Yu
5263a9e364 ac,radeonsi: remove unused ps prolog key fields
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24989>
2023-10-10 11:10:20 +08:00
Qiang Yu
1517aa7a8a aco,radv: add radeonsi spec ps epilog code
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24973>
2023-10-10 02:36:34 +00:00
Friedrich Vock
2be9b66cdd radv: Fix check in insert_block
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25496>
2023-10-01 13:11:50 +02:00
Friedrich Vock
a0fba17311 radv: Initialize shader freelist on allocation
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25496>
2023-10-01 13:11:43 +02:00
Samuel Pitoiset
fae4360a08 radv: enable lowering of mesh/task shader queries when enabled
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
2023-09-26 07:50:16 +00:00
Samuel Pitoiset
57dec0678e ac/nir: add lowering for mesh shader queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25331>
2023-09-26 07:50:15 +00:00
Connor Abbott
c93bcb32fe amd: Use inverse ballot intrinsic if available
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>
2023-09-20 14:41:18 +00:00
Connor Abbott
4282386311 nir/spirv: Add inverse_ballot intrinsic
This is actually a no-op on AMD, so we really don't want to lower it to
something more complicated.  There may be a more efficient way to do
this on Intel too. In addition, in the future we'll want to use this for
lowering boolean reduce operations, where the inverse ballot will
operate on the backend's "natural" ballot type as indicated by
options->ballot_bit_size, instead of uvec4 as produced by SPIR-V. In
total, there are now three possible lowerings we may have to perform:

- inverse_ballot with source type of uvec4 from SPIR-V to inverse_ballot
with natural source type, when the backend supports inverse_ballot
natively.
- inverse_ballot with source type of uvec4 from SPIR-V to arithmetic,
when the backend doesn't support inverse_ballot.
- inverse_ballot with natural source type from reduce operation, when
the backend doesn't support inverse_ballot.

Previously we just did the second lowering unconditionally in vtn, but
it's just a combination of the first and third. We add support here for
the first and third lowerings in nir_lower_subgroups, instead of simply
moving the second lowering, to avoid unnecessary churn.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>
2023-09-20 14:41:18 +00:00
Rhys Perry
2965a9d510 radv: optimize mesh workgroup ID using ts_mesh_dispatch_dimensions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24882>
2023-09-12 14:31:07 +00:00
Konstantin Seurer
ce4c38ecae radv: Only generate debug info if required
Fixes: 51f2fa1a5e ("radv: Break up radv_shader_nir_to_asm")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
2023-09-01 07:23:33 +00:00
Georg Lehmann
9cf6984200 nir: unify lower_find_msb with has_{find_msb_rev,uclz}
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>
2023-08-22 12:08:37 +00:00
Georg Lehmann
2ac7e6614a nir: unify lower_bitfield_extract with has_bfe
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>
2023-08-22 12:08:37 +00:00
Georg Lehmann
34c3f81614 nir: unify lower_bitfield_insert with has_{bfm,bfi,bitfield_select}
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>
2023-08-22 12:08:37 +00:00
Samuel Pitoiset
6ad8abf7aa radv: use the maximum possible workgroup size for TCS epilogs
It's similar to when the patch control points value is dynamic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
2023-08-22 06:10:32 +00:00
Caio Oliveira
39e24082fc radv: Use nir_opt_reuse_constants()
Right now, this won't change much the shaders since most of the NIR constants
are reused in the NIR generated by SPIR-V, but will make radv resilient to
when that behavior change.

```
RADV GFX1100 results for radv fossils:

Totals:
Instrs: 71623585 -> 71623708 (+0.00%); split: -0.00%, +0.00%
CodeSize: 369326156 -> 369324312 (-0.00%); split: -0.00%, +0.00%
SpillSGPRs: 13576 -> 13586 (+0.07%)
Latency: 632889681 -> 632887831 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 81674616 -> 81674859 (+0.00%); split: -0.00%, +0.00%
SClause: 2409601 -> 2409593 (-0.00%); split: -0.00%, +0.00%
Copies: 4063438 -> 4063579 (+0.00%); split: -0.00%, +0.01%
Branches: 1196703 -> 1196723 (+0.00%)
PreSGPRs: 4242897 -> 4243061 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 3926739 -> 3926742 (+0.00%)

Totals from 217 (0.16% of 133461) affected shaders:
Instrs: 353567 -> 353690 (+0.03%); split: -0.04%, +0.07%
CodeSize: 1790200 -> 1788356 (-0.10%); split: -0.15%, +0.04%
SpillSGPRs: 8 -> 18 (+125.00%)
Latency: 5152817 -> 5150967 (-0.04%); split: -0.05%, +0.01%
InvThroughput: 664273 -> 664516 (+0.04%); split: -0.03%, +0.06%
SClause: 10164 -> 10156 (-0.08%); split: -0.10%, +0.02%
Copies: 24225 -> 24366 (+0.58%); split: -0.32%, +0.90%
Branches: 7116 -> 7136 (+0.28%)
PreSGPRs: 13351 -> 13515 (+1.23%); split: -0.16%, +1.39%
PreVGPRs: 11583 -> 11586 (+0.03%)
```

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>
2023-08-17 14:58:02 +00:00
Faith Ekstrand
6c1d32581a nir: Drop nir_alu_dest
Instead, we replace it directly with nir_def.  We could replace it with
nir_dest but the next commit gets rid of that so this avoids unnecessary
churn.  Most of this commit was generated by sed:

   sed -i -e 's/dest.dest.ssa/def/g' src/**/*.h src/**/*.c src/**/*.cpp

There were a few manual fixups required in the nir_legacy.c and
nir_from_ssa.c as nir_legacy_reg and nir_parallel_copy_entry both have a
similar pattern.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
2023-08-14 21:22:53 +00:00
Samuel Pitoiset
1b66ebf09a radv/rt: fix capture/replay support
When replaying a RT pipeline, RADEON_FLAG_REPLAYABLE should be set.

The idea is that for capture, RADEON_FLAG_REPLAYABLE should be passed
when allocating a BO (ie. replay_va would be 0), and then for replay
the VA would be non-zero but the flag is also required.

Fixes
dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.multithreaded_compilation.*.

Fixes: 744357477e ("radv: Add utilities to serialize and deserialize shader allocation info")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24543>
2023-08-08 18:07:22 +00:00
Samuel Pitoiset
44e82a6cf1 radv: add a helper to get the maximum number of scratch waves per shader
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24502>
2023-08-08 09:28:54 +00:00
Samuel Pitoiset
8abf8dad6b radv: add infra for creating TCS epilogs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24404>
2023-08-02 16:59:18 +00:00
Danylo Piliaiev
261df5fb3c radv: Use common nir_vk_is_not_xfb_output
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24318>
2023-08-01 10:32:02 +02:00
Danylo Piliaiev
81407797b9 radv: fix unused non-xfb shader outputs not being removed
It was not taken into account that without Offset decoration
the output is not written into XFB.

Aside from eliminating more outputs this change prevents gl_PerVertex
builtins generated by glslang from being kept alive in case when XFB
is enabled. Keeping such outputs alive may upset a driver.

VUID-StandaloneSpirv-Offset-04716:
    "Only variables or block members in the output interface decorated
    with Offset can be captured for transform feedback, and those
    variables or block members must also be decorated with XfbBuffer
    and XfbStride, or inherit XfbBuffer and XfbStride decorations from
    a block containing them"

Additional info about glslang behavior could be found at:
 https://github.com/KhronosGroup/glslang/issues/1526

Fixes: e95531e101
("radv: fix gathering XFB info if there is dead outputs")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24318>
2023-08-01 10:30:59 +02:00
Rhys Perry
76232d6724 radv: correctly skip MRT output NaN fixup for meta shaders
radv_nir_compiler_options::enable_mrt_output_nan_fixup is only used for
epilogs, these days.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 290c3d360e ("aco,radv: lower outputs to exports when nir for monolithic ps")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9414
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24352>
2023-07-31 17:31:00 +00:00
Rhys Perry
e88c077096 radv: workaround WWZ exporting index=1 through location=1
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 290c3d360e ("aco,radv: lower outputs to exports when nir for monolithic ps")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9232
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24354>
2023-07-31 11:38:14 +00:00
Samuel Pitoiset
e1f8cfc2b2 radv: rename NGG query state to be more generic
To use emulated GS counters for legacy GS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24231>
2023-07-27 09:13:11 +02:00
Samuel Pitoiset
08bfcc12d4 radv: rename radv_pipeline_stage to radv_shader_stage
It's more generic and it will fit shader object just well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24313>
2023-07-26 07:44:49 +00:00
Daniel Schürmann
7e4870e8e5 amd: Do shader binary alignment for prefetch at memory allocation time.
This makes it consistent between drivers and compilers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23799>
2023-07-11 12:01:45 +00:00
Daniel Schürmann
437bf4fccb amd: move end-of-code marker padding to ACO.
This makes it consistent between drivers and compilers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23799>
2023-07-11 12:01:45 +00:00
Daniel Schürmann
e88c0bb945 radv: migrate radv_shader hash to BLAKE3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23974>
2023-07-11 09:02:43 +00:00
Jesse Natalie
511116d630 radv: Fix label name
Reviewed-by: Eric Engestrom <eric@igalia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24042>
2023-07-07 17:40:38 +00:00
Friedrich Vock
e3bd54d2a8 radv: Add support for creating capture/replay shaders
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
2023-07-05 15:58:25 +00:00
Friedrich Vock
4f192b9af4 radv: Split up implementation of radv_shader_create
This will make it easy to re-use the split-up parts for creating
replayed shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
2023-07-05 15:58:25 +00:00
Friedrich Vock
51f2fa1a5e radv: Break up radv_shader_nir_to_asm
radv_shader_nir_to_asm actually had 3 functions: compiling the NIR to
asm, uploading the shaders and generating debug info for them.
This reduces the functionality of radv_shader_nir_to_asm to only compile
NIR to asm. Uploading the shader and generating debug info is split into
separate functions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
2023-07-05 15:58:25 +00:00
Friedrich Vock
878a731c77 radv: Add radv_shader_reupload
Used for relocating RT shaders with capture/replay.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
2023-07-05 15:58:24 +00:00
Friedrich Vock
744357477e radv: Add utilities to serialize and deserialize shader allocation info
Can be used to capture/replay an arbitrary sequence of shader
allocations while preserving VAs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
2023-07-05 15:58:24 +00:00
Friedrich Vock
d23e41de6c radv: Add option to allocate shaders in replayable VA range
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23516>
2023-07-05 15:58:24 +00:00