The Mesh pipeline is implemented as a variant of the
regular (primitive) Graphics Pipeline.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
This is a nontrivial chunk of code that makes for a nice dis/assembler test
case (and caught a bug already...). Add it to the observatory.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
The swizzle handling in ISA.xml was broken in a bunch of place. Now that
we've fixed these issues, let's add tons of tests to validate.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two
bytes. The definition is the same as Bifrost. Let's call this a half-swizzle
since we need a name, and it is indeed half a swizzle...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
The lane select is in bit 28, this is covered by the "16-bit swizzle" mode.
However, the source type isn't inferred from the name in valhall.py, so
explicitly annotate the source as 16-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Per primitive & attachment shading rate support added.
v2: Rebase on KHR_dynamic_rendering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
For instance, the current code in genX_cmd_buffer.c assumes that the
depth/stencil attachments & resolves will be at the end of all
attachments, but that won't be the case anymore with fragment rate
shading.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.
v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)
v3: Drop unused macro (Nanley)
s/isl_to_gen/isl_encode/ (Nanley)
Remove pitch alignment 128B constraint already covered by tiling (Nanley)
Move some asserts together (Nanley)
v4: Disable miptail for now (Nanley)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
DG2 introduces per primitive coarse pixel settings (in stages
preceding the PS shader) and also a control surface specifying the
rate at through the resulting surface.
v2: update comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Recursive "loops" tend to be more difficult to follow
and understand. Additionally iterative approach should be
nicer for compiler. (Less to allocate on stack and easier to optimize)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13226>
Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
The assert for the TiledSurface field caught a programming error, but
with a segfault instead of the usual route of assert-failing. We only
set this field when we have a depth surface, but we also need to set it
when one isn't provided. Fix this issue and drop the assert.
Fixes: b77d694223 ("intel/isl: Allow HiZ with Tile4/64 surfaces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
There should be no visible functional change. Although an unrelated
change in the codegen replaced vn_info_extension_spec_version by
vn_info_extension_get. We have to adapt to that.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14782>
I was tired of swapping gpus around just to check shader-db results of MRs
for these. I put it in src/amd since it doesn't make sense in either of
r300 or r600.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809>
We already had them disabled for hwtcl, but in the swtcl case gallivm's
param query would return (nir) support even though nir-to-tgsi couldn't
handle it because TGSI doesn't do fp16/int16.
Fixes: 7d2ea9b0ed ("r300: Request NIR shaders from mesa/st and use NIR-to-TGSI.")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809>
