Only ARF sources are relevant in this case, so check the file
before calling size_read().
Below are fossil compilation times in a MTL machine compiling shaders
for a BMG GPU:
```
// Differences at 95.0% confidence.
// Rise of the Tomb Raider (n=20)
No difference proven
// Alan Wake (n=20)
-0.0725 +/- 0.0139437
-2.30965276% +/- 0.438787%
// Borderlands 3 (n=14)
-0.248571429 +/- 0.135107
-1.76946153% +/- 0.954171%
// Oblivion Remastered (n=14)
-0.0735714286 +/- 0.0235712
-1.54770849% +/- 0.492117%
// Baldur's Gate 3 (n=14)
-0.832142857 +/- 0.23095
-1.98028217% +/- 0.545648%
```
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41496>
regs_read() itself gets inlined, but size_read() does not. In GCC
release builds this results in three calls to size_read() at each site,
one of them due to how MIN2 is expanded. Use a local variable to store
the result.
Below are fossil compilation times in a MTL machine compiling shaders
for a BMG GPU:
```
// Differences at 95.0% confidence.
// Rise of the Tomb Raider (n=20)
-0.013 +/- 0.00596452
-2.56410256% +/- 1.15623%
// Alan Wake (n=20)
-0.1755 +/- 0.0144896
-5.29491628% +/- 0.425556%
// Borderlands 3 (n=14)
-0.562142857 +/- 0.129678
-3.84765816% +/- 0.870239%
// Oblivion Remastered (n=14)
-0.0821428571 +/- 0.0262485
-1.69867061% +/- 0.537247%
// Baldur's Gate 3 (n=14)
-1.61357143 +/- 0.21693
-3.69788342% +/- 0.486462%
```
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41496>
The instruction may get transformed, modifying the destination before
the loop index gets incremented. So save the original regs_written
value to be used in the loop increment.
While we are here, assert that all the slots in mov[] are filled
at this point in the code.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41496>
On Xe2+ the Wa_1407528679 NoMask workaround is disabled, so
baked_ordered_dependency_mode() should treat all instructions as
exec_all, matching the logic in gather_inst_dependencies() and
emit_inst_dependencies().
Without this, ordered RegDist dependencies from uniform/WE_all
producers (e.g. 'mov s0, imm') are not found during baking and
fall through as separate WE_all SYNC NOPs. Real shaders pile up
dozens of these in front of masked sends.
v2(Caio): Fix existing scalar_register test expectations
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Fixes: 47a6ef3fef ("brw/scoreboard: Use a predicate helper for the nomask workaround")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41713>
Add two tests verifying that ordered RegDist dependencies from
uniform/WE_all producers are baked into the consumer's SWSB on Xe2+.
Disabled for now since they fail on current main.
Reviewed-by: Michael Cheng <michael.cheng@intel.com>
Assisted-by: Pi coding agent (Opus-4.7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41713>
CSE should not depend on liveliness analysis. When the pass runs the
only possible liveliness analysis that is run is on the bi_validate
path, having a dependency only makes our validated runs different (and
slower) than the unvalidated runs.
Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Found-by: Ryan Zhang <ryan.zhang@nxp.com>
Reviewed-by: Ryan Zhang <ryan.zhang@nxp.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41504>
CSE can cause some cases where we had
%3 = ICMP_OR %1, %2, 0
%4 = ICMP_OR %1, %2, 0
%5 = LSHIFT_AND %3, %4
To become
%3 = ICMP_OR %1, %2, 0
%5 = LSHIFT_AND %3, %3
The va_fuse_cmp pass would try to rewrite this as
%3 = ICMP_AND %1, %2, %3
But this is obviously wrong, we should not fuse the same instruction
together.
Fixes: 800a861431 ("pan/bi: Fuse FCMP/ICMP on Valhall")
Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Found-by: Ryan Zhang <ryan.zhang@nxp.com>
Reviewed-by: Ryan Zhang <ryan.zhang@nxp.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41504>
Zink now unconditionally requires VK_KHR_maintenance5 to run.
Add it to the required extension list of Zink documentation.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41729>
VK_KHR_maintenance5 is now unconditionally required by Zink.
Move it to the gl21_baseline capabilities set to make it required by
every Zink profile.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41729>
Fixes "multiple stores to the same location" assertions in tests like
dEQP-VK.pipeline.monolithic.color_write_enable_maxa.cwe_after_bind.attachments3_more0
In that case, the stores were actually to different locations, but some
constant additions hadn't been folded into the location field yet.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
jay is trying to use the fragment shader dispatch mask for helper
invocation lowering, but it was using load_sample_mask_in for that
(now load_coverage_mask_intel). But this isn't the MSAA coverage
mask, the two are different payload fields.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
We want it to be set to wherever the push constants ended up.
Setting it close to the setup_payload_push() call makes this easier.
We'll also be adding some extra UGPRs for the fragment shader payload
soon, and the partitioning code will just have one big UGPR partition
for payload fields, push constants, and general purpose UGPRs, so it
really won't know how to do this very well without duplicating a bunch
of information.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
The documentation is large and hard to follow due to all the optional
fields and the SIMD16 vs. SIMD32 split for barycentrics. This quick
summary helps clarify what fields exist, which are split for SIMD32
or kept together, and which pairs of registers are involved for splits.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
Constructing the render target store payload is more complex than we can
reasonably handle at the NIR level. The main reason is that samplemask
and stencil are packed 16-bit and 8-bit parameters, respectively, which
are intermixed with other values that are 32-bit. In SIMD32 mode, the
packed sub-32-bit values take up fewer registers than normal values.
Currently we also don't specialize the NIR for each FS dispatch width,
and we can't construct the message descriptor without knowing it.
So, we alter nir_intrinsic_store_render_target_intel to take each of
the expected parameters - colour, depth, stencil, samplemask,
src0_alpha, and discard predicate. We construct the payloads and
descriptors in the backend.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
Implement a simple pre-RA bottom-up list scheduler with the goal of decreasing
register pressure. On Xe2, this significantly reduces spilling.
SSA form allows us to estimate register demand cheaply and accurately, which
theoretically [1] gives this algorithm the two Hippocratic properties:
1. Shaders with low register pressure are unaffected.
2. Register pressure can only be decreased, never increased.
In other words: first, do no harm.
The heuristic itself is very simple: greedily choose instructions that decrease
liveness using a backwards list scheduler. This is far from optimal! But thanks
to the above properties, even a heuristic that picked random instructions would
be a win overall - by construction, we can only ever win.
In other words: this scheduler is your older brother powering off the game
console any time he's about to lose a game, maintaining a 100% win rate.
[1] In reality, neither property is strictly satisfied due to the messy details
of mapping our clean logical model onto Intel's many weird physical register
files. Nevertheless, the algorithm is well-motivated and the empirical results
on Xe2 are excellent.
SIMD16:
Totals:
Instrs: 2754194 -> 2753957 (-0.01%); split: -0.23%, +0.22%
CodeSize: 41094768 -> 41092768 (-0.00%); split: -0.23%, +0.23%
Number of spill instructions: 1724 -> 1129 (-34.51%)
Number of fill instructions: 1912 -> 1119 (-41.47%)
Totals from 168 (6.35% of 2647) affected shaders:
Instrs: 850994 -> 850757 (-0.03%); split: -0.75%, +0.73%
CodeSize: 12825680 -> 12823680 (-0.02%); split: -0.74%, +0.73%
Number of spill instructions: 1724 -> 1129 (-34.51%)
Number of fill instructions: 1912 -> 1119 (-41.47%)
SIMD32:
Totals:
Instrs: 4688858 -> 4557800 (-2.80%); split: -3.53%, +0.74%
CodeSize: 70177200 -> 68214816 (-2.80%); split: -3.53%, +0.74%
Number of spill instructions: 50316 -> 45795 (-8.99%); split: -9.56%, +0.57%
Number of fill instructions: 51526 -> 45075 (-12.52%); split: -13.23%, +0.71%
Totals from 819 (30.94% of 2647) affected shaders:
Instrs: 3810182 -> 3679124 (-3.44%); split: -4.35%, +0.91%
CodeSize: 57044000 -> 55081616 (-3.44%); split: -4.35%, +0.91%
Number of spill instructions: 49264 -> 44743 (-9.18%); split: -9.76%, +0.58%
Number of fill instructions: 50182 -> 43731 (-12.86%); split: -13.58%, +0.73%
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
logically it doesn't matter because we'll bail on a later check, but this is
still UB and therefore releases nasal demons.
i am jealous of Faith's Rust compilers. there, I said it.
==107281== Conditional jump or move depends on uninitialised value(s)
==107281== at 0x7069768: propagate_backwards (jay_opt_propagate.c:327)
==107281== by 0x7069768: jay_opt_propagate_backwards (jay_opt_propagate.c:367)
==107281== by 0x7058960: jay_compile (jay_from_nir.c:2677)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
Challenging to hit but fixes
dEQP-GLES3.functional.shaders.swizzle_math_operations.vector_multiply.mediump_ivec4_wzyx_zyxw_fragment
with scheduling changes.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
on top of scheduler changes, compile-time of shaders/blender/1017.shader_test:
Difference at 95.0% confidence
-0.00173202 +/- 0.00116931
-0.791537% +/- 0.532384%
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
We generalize the sample_mask_in lowering to handle this too.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41688>
Modify empty initializer list to use a zero initializer so we aren't
relying on the gnu extension.
Fixes: 690d9b0d00 ("util/u_trace: Rework resource management")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41715>
Some video decoders spit out AFBC(32x8,sparse) images. Advertise
support for this modifier so we can import such images.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40886>
AFBC has a number of superblock sizes and valid layouts, with differing
combinations allowed.
It's quite clear that 16x16 is ambivalent about whether or not
block-split mode is used. 64x4 prohibits block-split mode, and 32x8
either requires or prohibits it depending on the format.
Add proper handling so we filter out the right combinations.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40886>
Reorder the AFBC modifier checking code to first query whether the
device can do the mode at all, then to query whether or not the format +
modifier is supported at all, then to query whether the specific image
usage is OK, then to query whether or not it's optimal.
This will come in useful later when we want to split modifier queries
into: can this modifier ever be used, what can this modifier be used
for, and is this the best modifier for this usage.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40886>
