Commit graph

13547 commits

Author SHA1 Message Date
Timur Kristóf
faba30a8f3 aco/optimizer: Optimize p_extract + v_mul_u32_u24 to v_mad_u32_u16.
This should perform the same but removes SDWA from the address
calculations in NGG culling shaders for example.

This is done because SDWA is no longer available on GFX11.

Fossil DB stats on GFX1100:
Totals from 36 (0.03% of 134913) affected shaders:
CodeSize: 300968 -> 300884 (-0.03%); split: -0.04%, +0.01%
Instrs: 60955 -> 60863 (-0.15%); split: -0.15%, +0.00%
Latency: 426809 -> 426819 (+0.00%); split: -0.06%, +0.06%
InvThroughput: 39076 -> 39025 (-0.13%); split: -0.14%, +0.01%
VClause: 1440 -> 1443 (+0.21%)
Copies: 5714 -> 5725 (+0.19%)

Fossil DB stats on GFX1100 with NGG culling enabled:
Totals from 60953 (45.18% of 134913) affected shaders:
VGPRs: 2273172 -> 2273160 (-0.00%)
CodeSize: 186401864 -> 186403036 (+0.00%); split: -0.00%, +0.00%
Instrs: 37038048 -> 36977353 (-0.16%); split: -0.16%, +0.00%
Latency: 146466770 -> 146350172 (-0.08%); split: -0.08%, +0.00%
InvThroughput: 15342790 -> 15228585 (-0.74%); split: -0.74%, +0.00%
VClause: 669662 -> 669665 (+0.00%)
Copies: 2972380 -> 2972482 (+0.00%); split: -0.01%, +0.01%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17924>
2023-01-16 19:27:39 +00:00
Timur Kristóf
171d76ded1 aco/optimizer: Add missing v_lshlrev condition to can_apply_extract.
This was already handled by apply_extract but missing from
can_apply_extract, therefore may not be properly applied everywhere.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17924>
2023-01-16 19:27:39 +00:00
Rhys Perry
aa6b2ec46a ac/nir: use store_buffer_amd's base index
This allows ACO to combine the addition into the store without checking
for wraparound.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
2023-01-16 17:25:51 +00:00
Rhys Perry
39c214769b aco: restore semantic_can_reorder for GS output stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
2023-01-16 17:25:51 +00:00
Rhys Perry
18d3e4fecd radv,aco: use ac_nir_lower_legacy_gs
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
2023-01-16 17:25:51 +00:00
Rhys Perry
c7cedaaee2 radv: implement GS load_ring_gsvs_amd/load_ring_gs2vs_offset_amd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
2023-01-16 17:25:51 +00:00
Friedrich Vock
684eee0748 radv/bvh: Prevent NANs when computing node cost
Otherwise the degenerate geometry workaround never triggers, leading to bad performance.

Fixes: 6f45c98b ("radv/bvh: Adjust sah cost based on depth")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20723>
2023-01-16 14:49:54 +00:00
Pierre-Eric Pelloux-Prayer
a48642400b ac: don't call ac_query_pci_bus_info from ac_query_gpu_info
Instead let each driver call it.

radeonsi ignores the error because it doesn't require correct
pci-bus info to work properly.

radv keeps the existing behavior and fails if the pci-bus infos
is missing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20645>
2023-01-16 10:27:15 +01:00
Pierre-Eric Pelloux-Prayer
6f533c4ee2 ac: add ac_query_pci_bus_info helper
No functional changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20645>
2023-01-16 10:27:15 +01:00
Pierre-Eric Pelloux-Prayer
91b0cc3fe3 ac/info: move pci bus info in a struct
And add a validity flag because there's no way to
tell if they're valid, unless for the caller of
drmGetDevice2.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20645>
2023-01-16 10:27:15 +01:00
Vinson Lee
6986332c80 radv: Fix memory leak.
Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable page going out of scope leaks the storage it points to.

Fixes: 8d0e6c02c7 ("radv: Add RMV tracing utilities")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20711>
2023-01-15 23:55:40 +00:00
Friedrich Vock
eab2c39951 radv/rt: Divide by the correct workgroup size
Improves build performance by around 25%.

Fixes: 9369b407 ("radv: Use PLOC for BVH building")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20717>
2023-01-15 23:33:33 +00:00
Konstantin Seurer
03105138f1 radv/rt: Get rid of accel struct null checks
Quake II RTX ray queries:

Totals from 7 (14.29% of 49) affected shaders:
CodeSize: 167220 -> 165560 (-0.99%)
Instrs: 31674 -> 31454 (-0.69%)
Latency: 385145 -> 596737 (+54.94%)
InvThroughput: 78837 -> 122005 (+54.76%)
Copies: 4740 -> 4667 (-1.54%); split: -1.60%, +0.06%
Branches: 1565 -> 1493 (-4.60%)
PreSGPRs: 488 -> 501 (+2.66%); split: -0.41%, +3.07%
PreVGPRs: 617 -> 620 (+0.49%)

Performance stays the same.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20539>
2023-01-15 21:30:21 +00:00
Konstantin Seurer
33166ba50b radv: Use the null accel struct instead of emitting 0
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20539>
2023-01-15 21:30:21 +00:00
Konstantin Seurer
31ca19589f radv: Create a null TLAS as meta state
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20539>
2023-01-15 21:30:21 +00:00
Konstantin Seurer
6d06964f8a radv: Add a helper for finding memory indices
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20539>
2023-01-15 21:30:21 +00:00
Jason Ekstrand
d3feccfa6f radv: Use the new NIR builder tex helpers for meta
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19480>
2023-01-13 20:25:01 +00:00
Bas Nieuwenhuizen
edca10e9c9 aco: Pass correct number of coords to Vega 1D LOD instruction.
If we pass a physical 2D texture descriptor we should also pass 2
coords. Otherwise it just uses the random content in the second
register which ends up funny sometimes.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20696>
2023-01-13 16:55:06 +01:00
Samuel Pitoiset
5b3fb44ecc radv: fix re-emitting RB+ when the non-compacted color format changes
If the previously emitted graphics pipeline uses the value A for
col_format_non_compacted and the new bound graphics pipeline uses B.

At bind time, radv_cmd_state::col_format_non_compacted will be set to
B and the rbplus flag will be dirtied. But if there is no draws and a
new graphics pipeline is bound with the same value as A, the next
draw will emit the rbplus state with B instead of A.

This can be basically triggered with meta operations after drawing
because the driver saves/restores the bound pipeline.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8073
Fixes: 11469f7553 ("radv: copy the non-compacted color format at pipeline bind time")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20692>
2023-01-13 13:57:40 +00:00
Samuel Pitoiset
ebec42d799 radv: fix hashing pipeline keys if RADV_PERFTEST=ngg_streamout is used
On GFX10-10.3, RADV_PERFTEST=ngg_streamout can be used to replace the
legacy path but it should be in the pipeline key. Otherwise, it's
possible to load legacy shaders from the cache instead of NGG.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20668>
2023-01-13 13:10:12 +00:00
Martin Roukala (né Peres)
aab08fc250 zink/ci: relocate radv testing from radv's gitlab-ci.yml
Zink testing should happen in the layered-backends stage, not the AMD
one.

Suggested-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20677>
2023-01-13 12:20:08 +00:00
Samuel Pitoiset
2a5d7f4926 radv: fix missing implementation of creating images from swapchains
These pNext structs are part of VK_KHR_swapchain which is core Vulkan
1.1 but they were missing. Loosely based on ANV.

Passed WSI CTS.

Cc: 22.3 mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7797
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20641>
2023-01-13 07:42:33 +00:00
Konstantin Seurer
18e91ad329 radv: Fix deadlock in radv_rmv_log_event_create
Fixes: 8d0e6c0 ("radv: Add RMV tracing utilities")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20636>
2023-01-12 21:23:39 +00:00
Friedrich Vock
0b081731cb radv/rmv: Capture names of pipelines but not command buffers
For command buffers, only scratch/upload bos are logged which cannot be attributed to command buffer handles.

Fixes: 5611ab25 ("radv: Add RMV tracing layer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20647>
2023-01-12 16:42:22 +00:00
Friedrich Vock
681871ade1 radv/rmv: Fix resource ids for name tokens
Fixes: 5611ab25 ("radv: Add RMV tracing layer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20647>
2023-01-12 16:42:22 +00:00
Rhys Perry
9112fe3c76 radv/gfx11: increase radeon_check_space for occlusion query begin
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20652>
2023-01-12 13:37:42 +00:00
Qiang Yu
c412b21d85 ac/nir/ngg: implement 16bit output streamout
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
cd22bf90e7 ac/nir/ngg: refine nogs outputs handling
Gather outputs in advance to save both output data and type. Output data
is used for streamout and gfx11 param export. Output type is used for
streamout latter.

The output info will also be used for nir vertex export in the future.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Singed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
69d11b6926 ac/nir/ngg: fix gs 16bit output uninitialized channel when gfx11
Fixes: abe2e99e9e ("ac/nir/ngg: gs support 16bit outputs")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
3c26fbc934 ac/nir/ngg: fix gs store output for no param offset slot when gfx11
When slot has no param offset, we should not emit store output for
them on gfx11.

Fixes: abe2e99e9e ("ac/nir/ngg: gs support 16bit outputs")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
b4695f78ad ac/nir/ngg: always reset output when gs emit vertex
Follow the spec, all outputs even not this stream need to be
reset after emit vertex.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
82f45dd5d4 ac/nir/ngg: assert no offset for nogs/gs output handling
As we does not support nogs/gs indirect output, so the offset
is always 0.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
4b0ace2585 ac/nir/ngg: gs store output use nir_ssa_def instead of nir_variable
Because we called nir_lower_io_to_temporaries which ensure the
store output and emit vertex in the same block.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
Qiang Yu
0224741ef6 ac/nir/ngg: gs save data type of outputs
Prepare to support 16bit streamout and remove nir_variable output.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20350>
2023-01-12 03:47:01 +00:00
David Heidelberg
55135dc82f ci/amd: increase number of stoney runners
Everything up and running.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20626>
2023-01-11 23:07:43 +00:00
Samuel Pitoiset
e11e68b56b radv,aco: fix enable_mrt_output_nan_fixup for RAGE2 again
Driver workarounds for game bugs can be easily broken. This one
shouldn't be applied to meta shaders and this restores previous logic.

Fixes: da32cbb5c6 ("aco: fix missing uses of MRT output flags")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20637>
2023-01-11 15:55:32 +00:00
Boris Brezillon
fa4e729165 vulkan/wsi: Prepare things for image to image blits
Right now, the WSI core supports copying WSI images to a linear buffer
for implementations that want the result in this form. This being said,
most of the blit logic can be re-used for image to image copies, and that's
exactly what we'll need if we want to hook-up DXGI swapchains in the
win32 WSI implementation. So let's rename a few fields so we no longer
imply that images are copied to a buffer, and the use_buffer_blit boolean
an enum so we can extend the implementation to support image -> image
copies.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16200>
2023-01-11 09:31:02 +00:00
Friedrich Vock
e624494c0f radv: Enable RMV tracing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17331>
2023-01-11 06:55:04 +00:00
Friedrich Vock
abf3bcd6ea radv: Add RMV resource tracking
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17331>
2023-01-11 06:55:04 +00:00
Friedrich Vock
5611ab25d1 radv: Add RMV tracing layer
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17331>
2023-01-11 06:55:04 +00:00
Friedrich Vock
8d0e6c02c7 radv: Add RMV tracing utilities
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17331>
2023-01-11 06:55:04 +00:00
Friedrich Vock
d816859ede radv: Use internal allocation helpers for internal allocations
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17331>
2023-01-11 06:55:04 +00:00
Georg Lehmann
2b28983c5d aco: Use NSA on GFX11 with more than 5 vaddr registers.
On GFX11 the first 4 vaddr are single registers and the last contains the remaining vector.
image_bvh64_intersect_ray has a special NSA layout.

Foz-DB GFX1100:
Totals from 2763 (2.05% of 134913) affected shaders:
VGPRs: 145884 -> 145056 (-0.57%); split: -1.03%, +0.46%
CodeSize: 18406864 -> 18326136 (-0.44%); split: -0.47%, +0.04%
MaxWaves: 76030 -> 76146 (+0.15%)
Instrs: 3559785 -> 3525287 (-0.97%); split: -0.97%, +0.00%
Latency: 44278460 -> 43303419 (-2.20%); split: -2.33%, +0.13%
InvThroughput: 4966295 -> 4914927 (-1.03%); split: -1.04%, +0.01%
VClause: 51755 -> 51991 (+0.46%); split: -0.05%, +0.50%
SClause: 105241 -> 105267 (+0.02%); split: -0.08%, +0.10%
Copies: 214141 -> 182419 (-14.81%); split: -14.82%, +0.01%
Branches: 69525 -> 69521 (-0.01%)
PreVGPRs: 120910 -> 120256 (-0.54%); split: -0.56%, +0.02%

No changes on Navi21.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20370>
2023-01-11 00:00:38 +00:00
Georg Lehmann
9538d523b6 aco: Validate GFX11 NSA correctly.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20370>
2023-01-11 00:00:38 +00:00
Georg Lehmann
9abe4850ba aco: Handle NSA with vectors in get_mimg_nsa_dwords.
No Foz-DB changes.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20370>
2023-01-11 00:00:38 +00:00
Rhys Perry
b1e59646de aco/gfx11: increase vgpr_limit to 256
fossil-db (gfx1100):
Totals from 280 (0.21% of 134574) affected shaders:
MaxWaves: 3124 -> 2846 (-8.90%); split: +3.46%, -12.36%
Instrs: 1139038 -> 1091407 (-4.18%); split: -4.18%, +0.00%
CodeSize: 5809332 -> 5486812 (-5.55%); split: -5.55%, +0.00%
VGPRs: 35004 -> 42864 (+22.45%); split: -1.85%, +24.31%
SpillSGPRs: 1896 -> 1865 (-1.64%); split: -2.37%, +0.74%
SpillVGPRs: 17807 -> 2382 (-86.62%)
Scratch: 2573312 -> 736256 (-71.39%)
Latency: 27470485 -> 17981296 (-34.54%); split: -34.54%, +0.00%
InvThroughput: 5606102 -> 6527051 (+16.43%); split: -4.19%, +20.61%
VClause: 32319 -> 19927 (-38.34%); split: -39.13%, +0.78%
SClause: 15014 -> 14897 (-0.78%); split: -0.95%, +0.17%
Copies: 102977 -> 93511 (-9.19%); split: -9.93%, +0.74%
Branches: 15164 -> 14969 (-1.29%)
PreSGPRs: 19132 -> 19014 (-0.62%)
PreVGPRs: 30494 -> 37460 (+22.84%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
2023-01-10 16:01:38 +00:00
Rhys Perry
6872f8d861 aco/gfx11: allow true 16-bit instructions to access v128+
It looks like the LLVM assembler promotes true 16-bit instructions to VOP3
in this case.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
2023-01-10 16:01:38 +00:00
Rhys Perry
254b178d5b aco: disallow SGPRS/constants with interpolation instructions
https://reviews.llvm.org/D137575

The VINTRP format cannot encode anything except VGPRs.

Reading VINTERPInstructions.td, looks like it's the same for GFX11.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
2023-01-10 16:01:38 +00:00
Rhys Perry
5af891a747 aco: add more opcodes to can_use_DPP()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
2023-01-10 16:01:38 +00:00
Rhys Perry
c3dd1931d9 aco: allow Builder::Result to be dereferenced
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20251>
2023-01-10 16:01:38 +00:00